- 21 Dec, 2018 15 commits
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Alexandre Belloni authored
Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning that there are 2 registers instead of one. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rafał Miłecki authored
Documentation has been recently updated specifying that pinctrl should be subnode of the CRU "syscon". Support that by using parent node for regmap and reading "offset" property from the DT. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rafał Miłecki authored
As pointed by Rob, CRU is a kind of block that can't be guaranteed to have everything exposed as subnodes. It's a set of various registers that aren't tied to any single device. It could be described much more accurately as MFD (Multi-Function Device). Some hardware blocks may indeed want to access a register or two of the CRU which requires describing it as the "syscon". While at it replace exmple node name with the standard "pinctrl" (also pointed out by Rob). Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Ludovic Desroches authored
In order to be aware of all changes related to at91 pinctrl drivers, merge the two entries. Make use of the opportunity to replace Atmel by Microchip. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Aisheng Dong authored
ARM64 SoC does not encourage people to add more finegrained SoC config options rather than a single ARCH_<family> in arch Kconfig. So this patch aims to break the dependency on SOC_IMX8QXP. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Masahiro Yamada authored
These are constant data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Ryder Lee authored
Remove prompts to make all pinctrl cores to non-visible symbols and make sure the target SoCs would be coupled with the corresponding cores. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com Acked-by: Sean Wang <sean.wang@kernel.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Arnd Bergmann authored
Without CONFIG_PM_SLEEP, we get annoying warnings about unused functions: drivers/pinctrl/qcom/pinctrl-msm.c:1082:12: error: 'msm_pinctrl_resume' defined but not used [-Werror=unused-function] static int msm_pinctrl_resume(struct device *dev) ^~~~~~~~~~~~~~~~~~ drivers/pinctrl/qcom/pinctrl-msm.c:1075:12: error: 'msm_pinctrl_suspend' defined but not used [-Werror=unused-function] static int msm_pinctrl_suspend(struct device *dev) Mark them as __maybe_unused to shut up the warning and silently drop the functions without having to add ugly #ifdefs. Fixes: 977d057a ("pinctrl: msm: Add sleep pinctrl state transitions") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Maxime Ripard authored
The pinctrl node can have multiple regulators for each of its GPIO banks. Add the property descriptions. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be configured in devicetree using groups = BOOTx or groups = CARDx. This makes the behavior consistent with other pins inside the same driver as well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers. Fixes: 0fefcb68 ("pinctrl: Add support for Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be configured in devicetree using groups = BOOTx or groups = CARDx. This makes the behavior consistent with other pins inside the same driver as well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers. Fixes: 6ac73095 ("pinctrl: add driver for Amlogic Meson SoCs") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
Rename the existing "gpio" function to "gpio_periphs". This makes it consistent with the "gpio_aobus" function. Also GXBB and GXL are also using the "gpio_periphs" naming, so this makes the code here consistent with other Amlogic pinctrl drivers. No functional changes since thee "gpio" function is currently not used. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
Rename the existing "gpio" function to "gpio_periphs". This makes it consistent with the "gpio_aobus" function. Also GXBB and GXL are also using the "gpio_periphs" naming, so this makes the code here consistent with other Amlogic pinctrl drivers. No functional changes since thee "gpio" function is currently not used. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N) only belong to the pin controller in the AO domain. With the current definition these pins cannot be referred to in .dts files as group (which is possible on GXBB and GXL for example). Add a separate "gpio_aobus" function to fix the mapping between the pin controller and the GPIO pins in the AO domain. This is similar to how the GXBB and GXL drivers implement this functionality. Fixes: 9dab1868 ("pinctrl: amlogic: Make driver independent from two-domain configuration") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N) only belong to the pin controller in the AO domain. With the current definition these pins cannot be referred to in .dts files as group (which is possible on GXBB and GXL for example). Add a separate "gpio_aobus" function to fix the mapping between the pin controller and the GPIO pins in the AO domain. This is similar to how the GXBB and GXL drivers implement this functionality. Fixes: 9dab1868 ("pinctrl: amlogic: Make driver independent from two-domain configuration") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 17 Dec, 2018 1 commit
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Martin Schiller authored
This patch is based on commit a86caa9b ("pinctrl: msm: fix gpio-hog related boot issues"). It fixes the issue that the gpio ranges needs to be defined before gpiochip_add(). Therefore, we also have to swap the order of registering the pinctrl driver and registering the gpio chip. You also have to add the "gpio-ranges" property to the pinctrl device node to get it finally working. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 16 Dec, 2018 1 commit
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Nathan Chancellor authored
Clang does not support this option: warning: unknown warning option '-Woverride-init'; did you mean '-Woverride-module'? [-Wunknown-warning-option] 1 warning generated. Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 14 Dec, 2018 2 commits
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Maxime Ripard authored
The Allwinner SoCs have on most of their GPIO banks a regulator input. This issue was mainly ignored so far because either the regulator was a static regulator that would be providing power anyway, or the bank was used for a feature unsupported so far (CSI). For the odd cases, enabling it in the bootloader was the preferred option. However, now that we are starting to support those features, and that we can't really rely on the bootloader for this, we need to model those regulators as such in the DT. This is slightly more complicated than what it looks like, since some regulators will be tied to the PMIC, and in order to have access to the PMIC bus, you need to mux its pins, which will need the pinctrl driver, that needs the regulator driver to be registered. And this is how you get a circular dependency. In practice however, the hardware cannot fall into this case since it would result in a completely unusable bus. In order to avoid that circular dependency, we can thus get and enable the regulators at pin_request time. We'll then need to account for the references of all the pins of a particular branch to know when to put the reference, but it works pretty nicely once implemented. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
Convert string compares of DT node names to use of_node_name_eq helper instead. This removes direct access to the node name pointer. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 13 Dec, 2018 1 commit
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Linus Walleij authored
Merge tag 'intel-pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v4.21-1 Switch to generic ->probe() callbacks. Simplify getting .driver_data. Code formatting fixes and headers clean up. Special case is the driver for Intel Cherryview SoC, where GPIO enabling bit was mistakenly cleared when pin gets freed. It's fixed now. The below commit went to v4.20-rc3, that's why duplication. - ad774315 MAINTAINERS: Add tree link for Intel pin control driver The following is an automated git shortlog grouped by driver: baytrail: - Code formatting fixes - simplify getting .driver_data broxton: - Code formatting fixes - Get rid of unneeded ->probe() stub cannonlake: - Code formatting fixes - Get rid of unneeded ->probe() stub cedarfork: - Replace acpi.h with mod_devicetable.h - Get rid of unneeded ->probe() stub cherryview: - Stop clearing the GPIO_EN bit from chv_gpio_disable_free - Add chv_gpio_clear_triggering() helper function - simplify getting .driver_data denverton: - Replace acpi.h with mod_devicetable.h - Get rid of unneeded ->probe() stub geminilake: - Code formatting fixes icelake: - Code formatting fixes - Get rid of unneeded ->probe() stub intel: - Unexport intel_pinctrl_probe() - simplify getting .driver_data lewisburg: - Replace acpi.h with mod_devicetable.h - Get rid of unneeded ->probe() stub MAINTAINERS: - Add tree link for Intel pin control driver merrifield: - include bits.h instead of bitops.h sunrisepoint: - Get rid of unneeded ->probe() stub
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- 07 Dec, 2018 6 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.21 (take two) - Two small fixes for RZ/N1.
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Masahiro Yamada authored
checkpatch.pl suggests to use SPDX license tag. I am happy to follow it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Chen-Yu Tsai authored
The A64 only has one TS (transport stream) controller. The datasheet also lists the function as TS_XXX instead of TS0_XXX. Rename the function names now before any there are any users. Fixes: 96851d39 ("drivers: pinctrl: add driver for Allwinner A64 SoC") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Chen-Yu Tsai authored
The A64 only has one CSI (camera sensor interface) controller. The datasheet also lists the function as CSI_XXX instead of CSI0_XXX. Rename the function names now before any there are any users. Fixes: 96851d39 ("drivers: pinctrl: add driver for Allwinner A64 SoC") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Nicholas Mc Guire authored
devm_kstrdup() may return NULL if internal allocation failed. Thus using label, name is unsafe without checking. Therefor in the unlikely case of allocation failure, sx150x_probe() simply returns -ENOMEM. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 9e80f906 ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Yangtao Li authored
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 05 Dec, 2018 3 commits
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Nicholas Mc Guire authored
devm_kasprintf() may return NULL on failure of internal allocation thus the assignment to .label is not safe if not checked. On error npcm7xx_gpio_of() returns negative values so -ENOMEM in the (unlikely) failure case of devm_kasprintf() should be fine here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 3b588e43 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Hans de Goede authored
Clearing the GPIO_EN bit from chv_gpio_disable_free is a bad idea and pinctrl-cherryview.c is the only Intel pinctrl driver doing something like this. Clearing the GPIO_EN bit means that if the pin was an output it is now effectively floating. The datasheet is not clear what happens to pull ups / downs in this case, but from testing it looks like these are disabled too, also floating input pins. One example where this is causing issues is the soc_button_array input driver, this parses ACPI tables to create 2 platform devices for the gpio_keys input driver. The list of GPIOs is passed through struct gpio_keys_platform_data which uses gpio numbers rather then gpio_desc pointers. The buttons handled by this drivers short the pin to ground when pressed and the volume buttons rely on the SoC's internal pull-up to pull the pin high when the button is not pressed. To get the gpio number, the soc_button_array code calls gpiod_get_index followed by a desc_to_gpio call and then gpiod_put on the gpio_desc. This last call causes chv_gpio_disable_free to clear the GPIO_EN bit. When the gpio_keys driver then loads next it gets the gpio_desc again causing the GPIO_EN bit to be set again and immediately reads the GPIO value which for the volume buttons reads 0 at this time, causing a spurious press of the volume buttons to get reported. Putting a small delay between the gpio_desc request and the read fixes this, I assume that this is caused by the pull-up being temporarily disabled while the GPIO_EN bit is cleared as the powerbutton which also has its GPIO_EN bit cleared does not have this problem. The soc_button_array code is not the only code temporarily requesting GPIOs the DWC3 PCI code also does this, to set the enable and reset GPIOs for the external phy, so that the code instantiating the ULPI phy can read the vendor and product ID registers from the phy. These GPIOs are released after this so that the PHY driver can claim and use them when it loads. Another example of temporary GPIO usage would be a user-space set_gpio utility using the userspace ioctls to set a GPIO as output value 0 or 1, having the GPIO revert to floating as soon as this utility exits would certainly be unexpected behavior. One argument in favor of clearing the GPIO_EN bit is if the GPIO is going to be muxed to another function after being released, but in that case chv_pinmux_set_mux() already clears it. TL;DR: Clearing the GPIO_EN bit from is a bad idea, this commit therefor removes the clearing from chv_gpio_disable_free(), replacing it with code to clear the interrupt-trigger condition so that the GPIO stops generating interrupts when released, as pinctrl-baytrail.c does. Note this commit adds a !chv_pad_locked() condition to the trigger clearing call, which the original GPIO_EN clearing code was missing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Hans de Goede authored
This is a preparation patch for clearing the interrupt trigger from chv_gpio_disable_free(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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- 04 Dec, 2018 2 commits
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Phil Edworthy authored
If we assign the result of of_get_child_count() to an unsigned int, the code will not detect any errors. Therefore assign it to an int instead. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Phil Edworthy authored
This fixes the check for unused mdio bus setting and the following static checker warning: drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select() warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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- 26 Nov, 2018 2 commits
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Shawn Guo authored
Let's add "qcom,pms405-gpio" to match table, as commit ed80f6eb ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") already adds the compatible. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Shawn Guo authored
Rather than gpio1-gpio11 for pms405, there are 12 GPIOs for pms405. But gpio1, gpio9 and gpio10 are not available. Fix the bindings doc to make it correct for pms405. Fixes: ed80f6eb ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 25 Nov, 2018 3 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.21-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.21 - Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W, - Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C, - Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3, - Add QSPI pin groups on R-Car V3M and V3H, - Add VIN and CAN(FD) pin groups on R-Car M3-N, - Add I2C[035] pin groups on R-Car H3 and M3-W, - Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC, - Small cleanups, - Maintainership updates.
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Mesih Kilinc authored
The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Mesih Kilinc authored
Add compatible string for Allwinner suniv F1C100s SoC's pinctrl. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 23 Nov, 2018 2 commits
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Chris Brandt authored
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Chris Brandt authored
Add device tree binding documentation and header file for Renesas R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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- 20 Nov, 2018 1 commit
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Dmitry Shifrin authored
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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- 19 Nov, 2018 1 commit
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Rob Herring authored
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-mediatek@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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