- 26 Sep, 2017 40 commits
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Roman Li authored
In some use-cases, e.g. multiple 4K displays, exisitng wait time for reg update of 30msec timed out during mode setiing that sometimes resulted in system bad state as we continue without waiting for registry update complete. Increasing timeout to 35msec fixes that problem. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Acked-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Register ISR hnadler on the new interrupt. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
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Andrey Grodzovsky authored
VBLANK interrupt is driven bu line buffer vcounter which is ahead of CRTC vcounter. Use an interrupt that fires at the actual CRTC vblank start boundry. Signed-off-by:
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Harry Wentland authored
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Yongqiang Sun authored
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xhdu authored
Leave hardcoded if no ContainerId provided by DM. Signed-off-by:
Duke Du <Duke.Du@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Charlene Liu authored
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Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Charlene Liu authored
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Leon Elazar authored
1. Locking all pipes before doing any changes 2. Applying surface for both top and bottom pipes Signed-off-by:
Leon Elazar <leon.elazar@amd.com> Acked-by:
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Andrey Grodzovsky authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
This will return back MAX cursor size for given ASIC. Signed-off-by:
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Andrey Grodzovsky authored
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Andrey Grodzovsky authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
ret value in amdgpu_dm_atomic_check was not rest to EINVAL after drm_atomic_add_affected_planes and by this making any subsequent validation failure pass when returning to atomic_check. v2: Add WARN_ON print for dc_commit_streams in amdgpu_dm_atomic_commit_tail since this should never fail. Signed-off-by:
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Tony Cheng authored
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Tony Cheng authored
- also some clean up Signed-off-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Leon Elazar authored
1. Adding the ability to update the stream parameters during FULL_UPDATE type Signed-off-by:
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Dmytro Laktyushkin authored
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Logatharshan Thothiralingam authored
[Problem] VSR greyed out [Root cause] When converting fractions, we were using the integer function, which let to a large display clock and the view was not supported [Solution] Change the integer to fraction functions Signed-off-by:
Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com> Acked-by:
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Leon Elazar authored
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Alex Deucher authored
Add the DC display module to drive the DCE12 IP on vega10. Signed-off-by: -
Alex Deucher authored
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Jordan Lazare authored
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Charlene Liu authored
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Alex Deucher authored
This wires DCE12 support into DC and enables it. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Viewport would be incorrectly adjusted when surface was used for multiple displays Signed-off-by:
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Jordan Lazare authored
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Dmytro Laktyushkin authored
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