- 07 Apr, 2022 6 commits
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Tom Rix authored
Smatch reports this issue hdcp1_execution.c:500:29: warning: function 'mod_hdcp_hdcp1_dp_execution' with external linkage has definition The storage-class-specifier extern is not needed in a definition, so remove it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tomasz Moń authored
Enabling gfxoff quirk results in perfectly usable graphical user interface on MacBook Pro (15-inch, 2019) with Radeon Pro Vega 20 4 GB. Without the quirk, X server is completely unusable as every few seconds there is gpu reset due to ring gfx timeout. Signed-off-by:
Tomasz Moń <desowin@gmail.com> Signed-off-by:
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Kai-Heng Feng authored
DP/HDMI audio on AMD PRO VII stops working after S3: [ 149.450391] amdgpu 0000:63:00.0: amdgpu: MODE1 reset [ 149.450395] amdgpu 0000:63:00.0: amdgpu: GPU mode1 reset [ 149.450494] amdgpu 0000:63:00.0: amdgpu: GPU psp mode1 reset [ 149.983693] snd_hda_intel 0000:63:00.1: refused to change power state from D0 to D3hot [ 150.003439] amdgpu 0000:63:00.0: refused to change power state from D0 to D3hot ... [ 155.432975] snd_hda_intel 0000:63:00.1: CORB reset timeout#2, CORBRP = 65535 The offending commit is daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)"). Commit 34452ac3 ("drm/amdgpu: don't use BACO for reset in S3 ") doesn't help, so the issue is something different. Assuming that to make HDA resume to D0 fully realized, it needs to be successfully put to D3 first. And this guesswork proves working, by moving amdgpu_asic_reset() to noirq callback, so it's called after HDA function is in D3. Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
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Alex Deucher authored
Drop the trailing vcn. Fixes: afc2f276 ("drm/amdgpu/vcn: add vcn support for vcn 3.1.2") Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Melissa Wen authored
"Pre-multiplied" is the default pixel blend mode for KMS/DRM, as documented in supported_modes of drm_plane_create_blend_mode_property(): https://cgit.freedesktop.org/drm/drm-misc/tree/drivers/gpu/drm/drm_blend.c In this mode, both 'pixel alpha' and 'plane alpha' participate in the calculation, as described by the pixel blend mode formula in KMS/DRM documentation: out.rgb = plane_alpha * fg.rgb + (1 - (plane_alpha * fg.alpha)) * bg.rgb Considering the blend config mechanisms we have in the driver so far, the alpha mode that better fits this blend mode is the _PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, where the value for global_gain is the plane alpha (global_alpha). With this change, alpha property stops to be ignored. It also addresses Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1734 v2: * keep the 8-bit value for global_alpha_value (Nicholas) * correct the logical ordering for combined global gain (Nicholas) * apply to dcn10 too (Nicholas) Signed-off-by:
Melissa Wen <mwen@igalia.com> Tested-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Simon Ser <contact@emersion.fr> Signed-off-by:
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Felix Kuehling authored
Use rcu_read_lock to read p->event_idr concurrently with other readers and writers. Use p->event_mutex only for creating and destroying events and in kfd_wait_on_events. Protect the contents of the kfd_event structure with a per-event spinlock that can be taken inside the rcu_read_lock critical section. This eliminates contention of p->event_mutex in set_event, which tends to be on the critical path for dispatch latency even when busy waiting is used. It also eliminates lock contention in event interrupt handlers. Since the p->event_mutex is now used much less, the impact of requiring it in kfd_wait_on_events should also be much smaller. This should improve event handling latency for processes using multiple GPUs concurrently. v2: Reschedule the worker periodically to avoid soft lockup warnings Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Sean Keely <Sean.Keely@amd.com> # v1 Tested-by:
Sanjay Tripathi <sanjay.tripathi@amd.com> Signed-off-by:
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- 06 Apr, 2022 8 commits
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Lv Ruyi authored
'dm_services.h' included in 'freesync,c' is duplicated, so remove one. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Signed-off-by:
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Alex Deucher authored
SMU takes clock limits in Mhz units. socclk and fclk were using 10 khz units in some cases. Switch to Mhz units. Fixes higher than required SoC clocks. Fixes: 97cf3299 ("drm/amd/pm: Removed fixed clock in auto mode DPM") Reviewed-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
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Dmytro Laktyushkin authored
[Why & How] Make dcn315 base its clock table off dcfclk rather than fclk. This change also adds some sanity checking to make sure an empty pmfw table does not result in invalid dal clocks. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Grigory Vasilyev authored
Variable igp_lane_info always is 0. 0 & any value = 0 and false. In this way, all сonditional statements will false. The code was leftover from when the code was ported from radeon where igp_lane_info was derived from the vbios on supported platforms. [update commit message - Alex] Signed-off-by:
Grigory Vasilyev <h0tc0d3@gmail.com> Signed-off-by:
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Tom Rix authored
Smatch reports these issues si_blit_shaders.c:31:11: warning: symbol 'si_default_state' was not declared. Should it be static? si_blit_shaders.c:253:11: warning: symbol 'si_default_size' was not declared. Should it be static? Both symbols are only used in si.c. Single file symbols should be static. So move the definition of si_default_state and si_default_size to si_blit_shader.h and change their storage-class-specifier to static. Remove unneeded si_blit_shader.c Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Benjamin Marty authored
Fixes crash on MST Hub disconnect. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1849 Fixes: ee2698cf ("drm/amd/display: Changed pipe split policy to allow for multi-display pipe split") Signed-off-by:
Benjamin Marty <info@benjaminmarty.ch> Signed-off-by:
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Guo Zhengkui authored
Replace `if (!ret)` with `else` for simplification. Signed-off-by:
Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by:
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Philip Yang authored
bo_adev is NULL for system memory mapping to GPU. Fixes: 30671b44 ("drm/amdgpu: fix TLB flushing during eviction") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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- 05 Apr, 2022 20 commits
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Anthony Koo authored
- Add options to allow for configurable PHY options during PSR active state - Remove unused versioning and git hash Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] Function to calculate scaling ratios can be called with invalid plane src/dest, causing a divide by zero. [HOW] Fail building scaling params if plane state src/dest rects are unpopulated Tested-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why & How] The dp_trace structure is self contained component designed for all dp trace, and the edp link trace should be a part of it; Suggested-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Aric Cyr authored
- [FW Promotion] Release 0.0.111.0 - Check for invalid input params when building scaling params - Move link_trace for edp to dp_trace - Fix missing-prototypes warning - Enable 3 plane for DCN 3.0 and 3.02 - Extract set stream attribute into link_hwss - Revert Power down hardware if timer not trigger - Add support for handling 128b/132b link training test request - Add configuration options for AUX wake work around - Remove underflow IRQ type - Add flip interval workaround for low FPS in some game - Remove assert for odm transition case Tested-by:
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Becle Lee authored
[Why] No declaration of hubp1_wait_pipe_read_start found in header file. [How] Add its declaration. Tested-by:
Becle Lee <becle.lee@amd.com> Signed-off-by:
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Krunoslav Kovac authored
[WHY&HOW] Increase num of bottom planes to 2. Note that DCN 3.03 is left out since it has max 2 planes. Tested-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] Extract set stream attribute into link_hwss as part of the link hwss refactor work. Tested-by:
George Shen <George.Shen@amd.com> Acked-by:
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Martin Leung authored
Tested-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] DP2.x added new enum values for UHBR link rates in link training test request for test automation. We need to add UHBR link rates test request support in preparation for compliance test automation. [how] added a function that translate test link rate to dc link rate. Call the translation function to decide the requested test link rate. Tested-by:
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Jimmy Kizito authored
[Why] Work around to try to wake unresponsive DP sinks may need to be adjusted for certain sinks. [How] Add options to disable work around or adjust time spent trying to wake unresponsive DPRX. Tested-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by:
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Angus Wang authored
[WHY] Feature using the underflow IRQ type reverted [HOW] Removed underflow IRQ type entry Tested-by:
Angus Wang <Angus.Wang@amd.com> Signed-off-by:
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Angus Wang authored
[WHY] Some games experience low FPS issues when FreeSync is on and VSync is toggled to half refresh rate. [HOW] First create a function to determine workaround conditions, which is when we detect 2 or more VSync interrupts between flips and a very short VSync to flip interval. We do the workaround during VSync interrupts and set the v_total_max and min to nominal. We also cleanup after we exit the game. Tested-by:
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Eric Bernstein authored
Remove assert that will hit during odm transition case, since this is a valid case. Tested-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
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Philip Yang authored
For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have stall invalid PTEs in TC because one cache line has 8 pages. Need always flush_tlb after updating mapping. Signed-off-by:
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Alex Deucher authored
Seems to cause a reboots or hangs on some systems. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1924 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1953 Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Haowen Bai authored
report by coccicheck: drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:1951:2-3: Unneeded semicolon Fixes: c543dcbe ("drm/amdgpu/vcn: Add VCN ras error query support") Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Signed-off-by:
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Aashish Sharma authored
Fix the kernel test robot warning below: drivers/gpu/drm/amd/amdgpu/../display/dmub/inc/dmub_cmd.h:2893:12: warning: variable 'temp' set but not used [-Wunused-but-set-variable] Replaced the assignment to the unused temp variable with READ_ONCE() macro to flush the writes. READ_ONCE() helps avoid the use of volatile and makes it obvious from the code that the read here is intentional. Also verified on x86 that the generated code is exactly the same as before. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Aashish Sharma <shraash@google.com> Signed-off-by:
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Marko Zekovic authored
SMI clock measure API is failing on NAVI12, because sysfs node for pp_dpm_vclk is not existing. Enable sysfs node for pp_dpm_vclk for NAVI12. v2: Also enable sysfs node for pp_dpm_dclk. Reviewed-by:
Marko Zekovic <Marko.Zekovic@amd.com> Signed-off-by:
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Christian König authored
Testing the valid bit is not enough to figure out if we need to invalidate the TLB or not. During eviction it is quite likely that we move a BO from VRAM to GTT and update the page tables immediately to the new GTT address. Rework the whole function to get all the necessary parameters directly as value. Signed-off-by:
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CHANDAN VURDIGERE NATARAJ authored
[Why] Below general protection fault observed when WebGL Aquarium is run for longer duration. If drm debug logs are enabled and set to 0x1f then the issue is observed within 10 minutes of run. [ 100.717056] general protection fault, probably for non-canonical address 0x2d33302d32323032: 0000 [#1] PREEMPT SMP NOPTI [ 100.727921] CPU: 3 PID: 1906 Comm: DrmThread Tainted: G W 5.15.30 #12 d726c6a2d6ebe5cf9223931cbca6892f916fe18b [ 100.754419] RIP: 0010:CalculateSwathWidth+0x1f7/0x44f [ 100.767109] Code: 00 00 00 f2 42 0f 11 04 f0 48 8b 85 88 00 00 00 f2 42 0f 10 04 f0 48 8b 85 98 00 00 00 f2 42 0f 11 04 f0 48 8b 45 10 0f 57 c0 <f3> 42 0f 2a 04 b0 0f 57 c9 f3 43 0f 2a 0c b4 e8 8c e2 f3 ff 48 8b [ 100.781269] RSP: 0018:ffffa9230079eeb0 EFLAGS: 00010246 [ 100.812528] RAX: 2d33302d32323032 RBX: 0000000000000500 RCX: 0000000000000000 [ 100.819656] RDX: 0000000000000001 RSI: ffff99deb712c49c RDI: 0000000000000000 [ 100.826781] RBP: ffffa9230079ef50 R08: ffff99deb712460c R09: ffff99deb712462c [ 100.833907] R10: ffff99deb7124940 R11: ffff99deb7124d70 R12: ffff99deb712ae44 [ 100.841033] R13: 0000000000000001 R14: 0000000000000000 R15: ffffa9230079f0a0 [ 100.848159] FS: 00007af121212640(0000) GS:ffff99deba780000(0000) knlGS:0000000000000000 [ 100.856240] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 100.861980] CR2: 0000209000fe1000 CR3: 000000011b18c000 CR4: 0000000000350ee0 [ 100.869106] Call Trace: [ 100.871555] <TASK> [ 100.873655] ? asm_sysvec_reschedule_ipi+0x12/0x20 [ 100.878449] CalculateSwathAndDETConfiguration+0x1a3/0x6dd [ 100.883937] dml31_ModeSupportAndSystemConfigurationFull+0x2ce4/0x76da [ 100.890467] ? kallsyms_lookup_buildid+0xc8/0x163 [ 100.895173] ? kallsyms_lookup_buildid+0xc8/0x163 [ 100.899874] ? __sprint_symbol+0x80/0x135 [ 100.903883] ? dm_update_plane_state+0x3f9/0x4d2 [ 100.908500] ? symbol_string+0xb7/0xde [ 100.912250] ? number+0x145/0x29b [ 100.915566] ? vsnprintf+0x341/0x5ff [ 100.919141] ? desc_read_finalized_seq+0x39/0x87 [ 100.923755] ? update_load_avg+0x1b9/0x607 [ 100.927849] ? compute_mst_dsc_configs_for_state+0x7d/0xd5b [ 100.933416] ? fetch_pipe_params+0xa4d/0xd0c [ 100.937686] ? dc_fpu_end+0x3d/0xa8 [ 100.941175] dml_get_voltage_level+0x16b/0x180 [ 100.945619] dcn30_internal_validate_bw+0x10e/0x89b [ 100.950495] ? dcn31_validate_bandwidth+0x68/0x1fc [ 100.955285] ? resource_build_scaling_params+0x98b/0xb8c [ 100.960595] ? dcn31_validate_bandwidth+0x68/0x1fc [ 100.965384] dcn31_validate_bandwidth+0x9a/0x1fc [ 100.970001] dc_validate_global_state+0x238/0x295 [ 100.974703] amdgpu_dm_atomic_check+0x9c1/0xbce [ 100.979235] ? _printk+0x59/0x73 [ 100.982467] drm_atomic_check_only+0x403/0x78b [ 100.986912] drm_mode_atomic_ioctl+0x49b/0x546 [ 100.991358] ? drm_ioctl+0x1c1/0x3b3 [ 100.994936] ? drm_atomic_set_property+0x92a/0x92a [ 100.999725] drm_ioctl_kernel+0xdc/0x149 [ 101.003648] drm_ioctl+0x27f/0x3b3 [ 101.007051] ? drm_atomic_set_property+0x92a/0x92a [ 101.011842] amdgpu_drm_ioctl+0x49/0x7d [ 101.015679] __se_sys_ioctl+0x7c/0xb8 [ 101.015685] do_syscall_64+0x5f/0xb8 [ 101.015690] ? __irq_exit_rcu+0x34/0x96 [How] It calles populate_dml_pipes which uses doubles to initialize. Adding FPU protection avoids context switch and probable loss of vba context as there is potential contention while drm debug logs are enabled. Signed-off-by:
CHANDAN VURDIGERE NATARAJ <chandan.vurdigerenataraj@amd.com> Reviewed-by:
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- 01 Apr, 2022 6 commits
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Lee Jones authored
This ensures userspace cannot prematurely clean-up the client before it is fully initialised which has been proven to cause issues in the past. Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Lee Jones <lee.jones@linaro.org> Reviewed-by:
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Ma Jun authored
Sync up header and implementation to use the same parameter names in function amdgpu_ring_init. ring_size -> max_dw, prio -> hw_prio Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Ma Jun <Jun.Ma2@amd.com> Signed-off-by:
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Ruili Ji authored
gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for GCR_GENERAL_CNTL Acked-by:
Prike Liang <Prike.Liang@amd.com> Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
Ruili Ji <ruiliji2@amd.com> Signed-off-by:
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Kent Russell authored
Since unique_id is only supported in PMFW 0x3A5300 and higher, we will only be able to use it inside Smu_Metrics_V3_t, which requires PMFW 0x3A4900 and higher. Remove the unique_id/serial_number references from the v1 and v2 tables to avoid any confusion, and return 0 if metrics_v1 or metrics_v2 are used to try to get the unique_id/serial_number. Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Melissa Wen authored
FPU documentation states that developers must not use DC_FP_START/END inside dml files, but use this macro to wrap calls to FPU functions in dc folder (outside dml folder). Therefore, this patch removes DC_FP_* wrappers from dml folder and wraps calls for these FPU operations outside dml, as required. Acked-by:
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Melissa Wen authored
dcn10_validate_bandwidth is only used on dcn10 files, but is declared in dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper inside DML folder and create an specific dcn10_validate_bandwidth in dcn10_resources that calls dcn_validate_bandwidth and properly wraps that FPU function with DC_FP_* macro. Acked-by:
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