- 10 Jun, 2015 21 commits
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Thomas Petazzoni authored
This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Thomas Petazzoni authored
All SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions. It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names. While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet. Signed-off-by:
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Thomas Petazzoni authored
This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by:
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Thomas Petazzoni authored
In order to be consistent with the datasheet and some other SoCs, this commit renames the SDIO pins of the Armada 39x from "sd" to "sd0". While this changes the DT binding, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet (so now is the right time to fix such things). Signed-off-by:
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Thomas Petazzoni authored
This commit makes the naming of SATA related MPP functions consistent accross SoCs by adjusting the Armada 39x definition to use "prsnt" instead of "present". Since only the subnames are changed, the DT binding is not modified at all. Signed-off-by:
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Thomas Petazzoni authored
This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by:
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Thomas Petazzoni authored
The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by:
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Thomas Petazzoni authored
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by:
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Thomas Petazzoni authored
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by:
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Thomas Petazzoni authored
There was an incorrect space in the definition of the function of one pin in the Armada 375 pinctrl driver, which this commit fixes. Signed-off-by:
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Thomas Petazzoni authored
There was a mistake in the definition of the functions for MPP48 on Marvell Armada XP. The second function is dev(clkout), and not tclk. Signed-off-by:
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Thomas Petazzoni authored
The latest version of the Armada XP datasheet no longer documents the VDD cpu_pd functions, which might indicate they are not working and/or not supported. This commit ensures the pinctrl driver matches the datasheet. Signed-off-by:
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Thomas Petazzoni authored
After updating to a more recent version of the Armada XP datasheet, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by:
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Thomas Petazzoni authored
After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by:
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Thomas Petazzoni authored
Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that. This DT binding change does not affect any of the in-tree users. Signed-off-by:
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Thomas Petazzoni authored
A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by:
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Ludovic Desroches authored
There is no reason to try to print groups associated to a function if get_function_groups returns an error. Moreover, it can lead to a NULL pointer dereference error. Signed-off-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
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Bjorn Andersson authored
Signed-off-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Bjorn Andersson authored
Signed-off-by:
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Antoine Tenart authored
Add comments for the SPI functions, to distinguish CLK, SDI, SDO and C{0,1,2,3}n. Signed-off-by:Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
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Antoine Tenart authored
Rename function ss0 to spi1 to be consistent with the other Berlin function names. Signed-off-by:
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- 04 Jun, 2015 3 commits
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Vishnu Patekar authored
A33 PIO has 7 ports which starts from PB and has two interrupt ports. Signed-off-by:
Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Fabio Estevam authored
PTR_ERR should access the value just tested by IS_ERR The semantic patch that makes this change is available in scripts/coccinelle/tests/odd_ptr_err.cocci. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Fabio Estevam authored
platform_driver does not need to set the owner field, as it will be populated by the driver core, so just remove it. The semantic patch that makes this change is available in scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by:
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- 02 Jun, 2015 5 commits
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Masahiro Yamada authored
There are two types for pinctrl maps: pinmux and pinconfig This debug message shows the number of maps of both types. The string "pinmux map" is not precise. Let's say "pinctrl map" instead. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> [also fixed %d -> %u] Signed-off-by:
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Masahiro Yamada authored
This array is only referenced in this file and never updated. Signed-off-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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Masahiro Yamada authored
This array is only referenced in this file. Signed-off-by:
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Hongzhou Yang authored
Since mt6397 is no need to support interrupt controller, I judged "interrupt-controller" property to skip it last patch. But the if judgement should on the contrary, this is a bug. And find of_property_read_bool is better for this case. So using of_property_read_bool instead of of_find_property. Also fix bug of misuse pointer. Signed-off-by:
Hongzhou Yang <hongzhou.yang@mediatek.com> Reviewed-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
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Hongzhou Yang authored
Add ies/smt support for MSDC3. Also fix ies bug for pin 106 and 107. Signed-off-by:
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- 01 Jun, 2015 7 commits
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Geert Uytterhoeven authored
Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Masahiro Yamada authored
Only this member, pins, is defined as "struct ... const *", but the others in this struct, pinlops, pmxops, confops, etc. are defined as "const struct ... *". Swap the "struct pinctrl_pin_desc" and "const" for consistency. Signed-off-by:
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Masahiro Yamada authored
This "const" claims the get_function_groups callback never changes the given num_groups pointer. It is always true in C language, so not worth mentioning. Signed-off-by:
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Masahiro Yamada authored
The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, 0xf8000834, respectively. Each offset address must be prefixed with 0x. Fixes: add958ce "pinctrl: Add driver for Zynq" Signed-off-by:
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Masahiro Yamada authored
The offset to the mux register is missing. Fixes: add958ce "pinctrl: Add driver for Zynq" Signed-off-by:
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Jon Hunter authored
Commit e5b3b2d9 ("pinctrl: allows not to define the get_group_pins operation") allows pin controllers not to register the get_group_pins() function. However, a side-effect of not registering this function is that pins are not allocated and potentially multiple devices could attempt to configure the same pins [1]. Although this problem exists in the pinctrl core, because only a few devices are impacted by this, fix this for tegra-xusb by adding the get_group_pins() function. Please note that in addition to adding the get_group_pins() functions the pins/lanes for the tegra-xusb also need to be registered when calling pinctrl_register(). This also allows the current pinmux state to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad controller. [1] http://www.spinics.net/lists/linux-gpio/msg05810.htmlSigned-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Jon Hunter authored
The structure tegra_xusb_padctl_group is defined but never used and so remove this. Signed-off-by:
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- 28 May, 2015 1 commit
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Linus Walleij authored
If we know we are using a strict pin controller (one that cannot mix device functions+group use and GPIO) we can be a bit more specific in debugfs, just print either device-function-group or GPIO consumer for the pin. Let's do that to be helpful. Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
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- 20 May, 2015 1 commit
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Linus Walleij authored
X86_64 allmodconfig screams like so: warning: (PINCTRL_MT6397) selects PINCTRL_MTK_COMMON which has unmet direct dependencies (PINCTRL && (ARCH_MEDIATEK || COMPILE_TEST) && OF) So add OF to dependencies to shut up this warning. Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:
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- 19 May, 2015 2 commits
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Yoshihiro Shimoda authored
Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by:
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Wei Chen authored
The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by:
Wei Chen <Wei.Chen@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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