- 23 May, 2018 8 commits
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Geert Uytterhoeven authored
The comment block explaining the rationale for static pins contains grammar errors. It appeared first in the pin control driver for R-Car H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later. Fix the grammar in all copies at once. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Niklas Söderlund authored
Signed-off-by:
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Takeshi Kihara authored
This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP pins for the R8A77990 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Takeshi Kihara authored
This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to the R8A77990 SoC. NOTE: I2C0 and I2C3 are not pin multiplexed. Signed-off-by: -
Takeshi Kihara authored
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch implements control of pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by:
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Takeshi Kihara authored
This patch adds initial pinctrl driver to support for the R8A77990 SoC. Signed-off-by:
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Takeshi Kihara authored
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC. Signed-off-by:
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- 16 May, 2018 11 commits
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Biju Das authored
Add PFC support for the R8A77470 SoC including pin groups for some on-chip devices such as SCIF and MMC. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Takeshi Kihara authored
This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by:Yoshihiro Kaneko <ykaneko0929@gmail.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Tested-by:
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Kieran Bingham authored
This patch adds pins, groups and functions for parallel RGB output signals from DU. The HDMI and TCON pins are added to separate groups. Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Thomas Gleixner authored
GPL-2. is not a valid SPDX identifier. Make it GPL-2.0 Fixes: 490e687e ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Rob Herring <robh@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Sergei Shtylyov authored
I've included the pin I/O voltage control into the R8A77970 PFC driver but it was incomplete because: - SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly; - sh_pfc_soc_info::ioctrl_regs wasn't set at all... Fixes: b92ac66a ("pinctrl: sh-pfc: Add R8A77970 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Add the pin I/O voltage level control support to the R8A77980 PFC driver. Loosely based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
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Biju Das authored
Document PFC support for the R8A77470 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Takeshi Kihara authored
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to R8A77965 SoC. Signed-off-by: -
Geert Uytterhoeven authored
Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
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Takeshi Kihara authored
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by:
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- 02 May, 2018 19 commits
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Dong Aisheng authored
For a constant format without additional arguments, use seq_puts() instead of seq_printf(). Also, it fixes the following checkpatch warning. WARNING: Prefer seq_puts to seq_printf + seq_printf(s, "N/A"); WARNING: Prefer seq_puts to seq_printf + seq_printf(s, "\n"); Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Dong Aisheng authored
The current code comments of PIN_FUNC_ID actually is not true for SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID. Fix the comments and re-org it a bit for better extendibility as we may add a different size for SCU based PIN_FUNC_ID later. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by:
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Dong Aisheng authored
The unsigned integer nfuncs is being error checked with a value less or equal to zero; this is always false if of_get_child_count returns a -ve for an error condition since nfuncs is not signed. Fix this by making variables nfuncs and i signed integers. Detected with Coccinelle: drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned expression compared with zero: nfuncs <= 0 Cc: Linus Walleij <linus.walleij@linaro.org> Reported-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Katsuhiro Suzuki authored
The MPEG2-TS input/output core both accepts serial TS and parallel TS. The serial TS interface uses following pins: hscin0_s : HS0DOUT[0-3] hscin1_s : HS0DOUT[4-7] hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0 hscout0_s: HS0DOUT[0-3] hscout1_s: HS0DOUT[4-7] And the parallel TS interface uses following pins: hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7] hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7] hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7] Signed-off-by:
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Katsuhiro Suzuki authored
The MPEG2-TS input/output core both accepts serial TS and parallel TS. The serial TS interface uses following pins: hscin0_s : HS0DOUT[0-3] hscin1_s : HS0DOUT[4-7] hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0 hscin3_s : HS1DIN[2-5] hscout0_s: HS0DOUT[0-3] hscout1_s: HS0DOUT[4-7] And the parallel TS interface uses following pins: hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7] hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7] hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7] Signed-off-by:
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Manivannan Sadhasivam authored
1. Fix Kconfig dependency for Actions Semi S900 pinctrl driver which generates below warning in x86: WARNING: unmet direct dependencies detected for PINCTRL_OWL Depends on [n]: PINCTRL [=y] && (ARCH_ACTIONS || COMPILE_TEST [=n]) && OF [=n] Selected by [y]: - PINCTRL_S900 [=y] && PINCTRL [=y] 2. Add help text for OWL pinctrl driver Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reported-by:
Randy Dunlap <rdunlap@infradead.org> Tested-by:
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Colin Ian King authored
There is a missing break in case PIN_CONFIG_DRIVE_STRENGTH leading to a fall-through to the PIN_CONFIG_SLEW_RATE case that performs different checks against *arg. This looks like an unintentional missing break so add in the break. Detected by CoverityScan, CID#1468456, 1468459 ("Missing break in switch") Fixes: 513d7a2f7e0f ("pinctrl: actions: Add Actions S900 pinctrl driver") Signed-off-by: -
Colin Ian King authored
s900_functions, s900_padinfo and s900_pads are local to the source and do not need to be in global scope, so make them static. Cleans up sparse warnings: drivers/pinctrl/actions/pinctrl-s900.c:1445:30: warning: symbol 's900_functions' was not declared. Should it be static? drivers/pinctrl/actions/pinctrl-s900.c:1664:20: warning: symbol 's900_padinfo' was not declared. Should it be static? drivers/pinctrl/actions/pinctrl-s900.c:207:31: warning: symbol 's900_pads' was not declared. Should it be static? Signed-off-by:
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Jerome Brunet authored
Add the information related to the tdm pins of the A113D SoC Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Martin Blumenstingl authored
These are only available on the Meson8m2 SoC (which uses the same DesignWare Ethernet MAC as Meson8b). The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII PHYs or the RGMII TX clock (as far as we know the frequency is controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP block). Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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Martin Blumenstingl authored
Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins, no other differences were found so far). Add the new compatible strings for Meson8m2 to the existing Meson8 driver so we don't have to duplicate the whole driver. Signed-off-by:
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Martin Blumenstingl authored
The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b (such as the Gigabit capable DesignWare MAC). It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins get an additional function (four of these are Ethernet RXD2, RXD3, TXD2 and TXD3 which are required when the board uses an RGMII PHY). The AOBUS pins seem to be identical on Meson8 and Meson8m2. Signed-off-by:
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Ryder Lee authored
Fulfill the pinmux macros for MT7623 Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Reviewed-by:
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Ricardo Silva authored
The pinctrl-mcp23s08 driver doesn't provide a specific gpiospec of_xlate() function, causing the gpiolib-of's of_gpio_simple_xlate() function to be used instead, which takes the gpiospec's second cell as the flags specifier according to 'include/dt-bindings/gpio/gpio.h'. The pinctrl-mcp23s08 bindings document was mentioning that the flags were unused, which is not accurate because values in that second cell are indeed used by the gpiolib-of's of_gpio_simple_xlate() for configuring the gpio (e.g. its polarity). This way, replace the "flags currently unused" reference in the dt-bindings document with references to the appropriate files specifying the possible flag values and gpiospec description. CC: devicetree@vger.kernel.org Signed-off-by:
Ricardo Silva <rjpdasilva@gmail.com> Reviewed-by:
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Matheus Castello authored
Added generic pin configuration and multiplexing support, and should be preferred than brcm legacy one. Signed-off-by:
Matheus Castello <matheus@castello.eng.br> Reviewed-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
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Timur Tabi authored
Newer versions of the firmware for the Qualcomm Datacenter Technologies QDF2400 restricts access to a subset of the GPIOs on the TLMM. To prevent older kernels from accidentally accessing the restricted GPIOs, we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002, and introduce a new property "gpios". This property is an array of specific GPIOs that are accessible. When an older kernel boots on newer (restricted) firmware, it will fail to probe. To implement the sparse GPIO map, we register all of the GPIOs, but fill in the data only for available GPIOs. This ensures that the driver cannot accidentally access an unavailable GPIO. The pinctrl-msm driver also scans the "gpios" property to determine which pins are available, and ensure that only those can be registered. Support for QCOM8001 is removed as there is no longer any firmware that implements it. Signed-off-by:
Timur Tabi <timur@codeaurora.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Timur Tabi authored
Two data structures are declared as static globals but are intended to be per-TLMM. Move them into the msm_pinctrl structure and initialize them at runtime. Signed-off-by:
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Manivannan Sadhasivam authored
Add pinctrl driver for Actions Semi S900 SoC. The driver supports pinctrl, pinmux and pinconf functionalities through a range of registers common to both gpio driver and pinctrl driver. Pinmux functionality is available only for the pin groups while the pinconf functionality is available for both pin groups and individual pins. Signed-off-by:
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Chanho Park authored
This patch adds a samsung_pin_dbg_show function to implement the pin_dbg_show callback function which can be used to show pin confuration values. Basically, it can show pin setting values by accessing the "pins" node like below: $ cat pins pin 0 (gpy7-0) CON(0x0) DAT(0x1) PUD(0x1) DRV(0x0) CON_PDN(0x0) PUD_PDN(0x0) Signed-off-by:
Chanho Park <parkch98@gmail.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Tested-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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- 16 Apr, 2018 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linuxLinus Torvalds authored
Pull more btrfs updates from David Sterba: "We have queued a few more fixes (error handling, log replay, softlockup) and the rest is SPDX updates that touche almost all files so the diffstat is long" * tag 'for-4.17-part2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux: btrfs: Only check first key for committed tree blocks btrfs: add SPDX header to Kconfig btrfs: replace GPL boilerplate by SPDX -- sources btrfs: replace GPL boilerplate by SPDX -- headers Btrfs: fix loss of prealloc extents past i_size after fsync log replay Btrfs: clean up resources during umount after trans is aborted btrfs: Fix possible softlock on single core machines Btrfs: bail out on error during replay_dir_deletes Btrfs: fix NULL pointer dereference in log_dir_items
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