- 30 Jun, 2021 11 commits
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Philip Yang authored
3 cases of kobj leak, which causes memory leak: kobj_type must have release() method to free memory from release callback. Don't need NULL default_attrs to init kobj. sysfs files created under kobj_status should be removed with kobj_status as parent kobject. Remove queue sysfs files when releasing queue from process MMU notifier release callback. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Philip Yang authored
No functionality change. Modify kfd_sysfs_create_file to use kobject as parameter, so it becomes common helper function to remove duplicate code and will simplify new kfd sysfs file create in future. Move pr_warn to helper function if sysfs file create failed. Set helper function as void return because caller doesn't use the helper function return value. Signed-off-by:
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Evan Quan authored
Avoid unnecessary register programming on feature disablement. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Evan Quan authored
Update GFX MGCG related settings. Signed-off-by:
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Evan Quan authored
Clock gating setting is still performed even when the corresponding CG feature is not supported. And the tricky part is disablement is actually performed no matter for enablement or disablement request. That seems not logically right. Considering HW should already properly take care of the CG state, we will just skip the corresponding clock gating setting when the feature is not supported. Signed-off-by:
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Evan Quan authored
SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by:
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Evan Quan authored
A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Signed-off-by:
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Evan Quan authored
Fix TCP hang when a lightweight invalidation happens on Navi1x. Signed-off-by:
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Evan Quan authored
Add missing settings for SQC bits. And correct some confusing logics around active wgp bitmap calculation. Signed-off-by:
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Chengzhe Liu authored
When unloading driver, if VCN is powered on, sending message DisableAllSmuFeatures to SMU will cause SMU hang. We need to power down VCN and JPEG before clean up SMU. Signed-off-by:
Chengzhe Liu <ChengZhe.Liu@amd.com> Reviewed-by:
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Zhan Liu authored
[Why] Sometimes, DP receiver chip power-controlled externally by an Embedded Controller could be treated and used as eDP, if it drives mobile display. In this case, we shouldn't be doing power-sequencing, hence we can skip waiting for T7-ready and T9-ready." [How] Added a feature mask to enable eDP no power sequencing feature. To enable this, set 0x10 flag in amdgpu.dcfeaturemask on Linux command line. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Signed-off-by:
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- 23 Jun, 2021 29 commits
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Dave Airlie authored
Merge tag 'amd-drm-next-5.14-2021-06-22-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-22-1: amdgpu: - Userptr BO fixes - RAS fixes - Beige Goby fixes - Add some missing freesync documentation - Aldebaran fixes - SR-IOV fixes - Potential memory corruption fix in framebuffer handling - Revert GFX9, 10 doorbell fixes, we just end up trading one bug for another - Multi-plane cursor fixes with rotation - LTTPR fixes - Backlight fixes - eDP fix - Fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN - Misc code cleanups amdkfd: - Topology fix - Locking fix radeon: - Misc code cleanup Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210622210345.27297-1-alexander.deucher@amd.com
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
* devcoredump support for display errors * dpu: irq cleanup/refactor * dpu: dt bindings conversion to yaml * dsi: dt bindings conversion to yaml * mdp5: alpha/blend_mode/zpos support * a6xx: cached coherent buffer support * a660 support * gpu iova fault improvements: - info about which block triggered the fault, etc - generation of gpu devcoredump on fault * assortment of other cleanups and fixes Signed-off-by:
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Rob Clark authored
This reverts commit c1d12c19. Breaks armv7 build ERROR: modpost: "__aeabi_ldivmod" [drivers/gpu/drm/msm/msm.ko] undefined! Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Dmitry Baryshkov authored
Instead of using static bandwidth setup, manage bandwidth dynamically, depending on the amount of allocated planes, their format and resolution. Co-developed-with: James Willcox <jwillcox@squareup.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210525131316.3117809-8-dmitry.baryshkov@linaro.orgSigned-off-by:
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James Willcox authored
Prior downstream kernels had "fudge factors" in devicetree which would be applied to things like interconnect bandwidth calculations. Bring some of those values back here. Signed-off-by:
James Willcox <jwillcox@squareup.com> [DB: changed _ff to _inefficiency, fixed patch description] Signed-off-by:
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Dmitry Baryshkov authored
Instead of implemeting zpos property on our own, use standard zpos property support. Signed-off-by:
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Dmitry Baryshkov authored
Hook alpha and pixel blend mode support to be exported as proper DRM plane properties. This allows using this functionality from the userspace. Signed-off-by:
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Dmitry Baryshkov authored
Use drm_plane_state's 'pixel_blend_mode' field rather than using 'premultiplied' field to mdp5_plane_state. Signed-off-by:
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Dmitry Baryshkov authored
Use drm_plane_state's 'alpha' field rather than adding extra 'alpha' field to mdp5_plane_state. Signed-off-by:
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Dmitry Baryshkov authored
Use generic helpers code to manage drm_plane_state part of mdp5_plane state instead of manually coding all the details. Signed-off-by:
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Dmitry Baryshkov authored
Move the call to dsi_mgr_phy_enable after checking whether the DSI interface is slave, so that PHY enablement happens together with the host enablement. Signed-off-by:
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Rob Clark authored
Just for the purposes of testing. Write to it the # of objects to scan, read back the # freed. Signed-off-by:
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Bjorn Andersson authored
Handling of the interrupt callback lists is done in dpu_core_irq.c, under the "cb_lock" spinlock. When these operations results in the need for enableing or disabling the IRQ in the hardware the code jumps to dpu_hw_interrupts.c, which protects its operations with "irq_lock" spinlock. When an interrupt fires, dpu_hw_intr_dispatch_irq() inspects the hardware state while holding the "irq_lock" spinlock and jumps to dpu_core_irq_callback_handler() to invoke the registered handlers, which traverses the callback list under the "cb_lock" spinlock. As such, in the event that these happens concurrently we'll end up with a deadlock. Prior to '1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")' the enable/disable of the hardware interrupt was done outside the "cb_lock" region, optimitically by using an atomic enable-counter for each interrupt and an warning print if someone changed the list between the atomic_read and the time the operation concluded. Rather than re-introducing the large array of atomics, this change embraces the fact that dpu_core_irq and dpu_hw_interrupts are deeply entangled and make them share the single "irq_lock". Following this step it's suggested that we squash the two parts into a single irq handling thing. Fixes: 1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling") Signed-off-by:Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
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Rob Clark authored
Wire up support to stall the SMMU on iova fault, and collect a devcore- dump snapshot for easier debugging of faults. Currently this is a6xx-only, but mostly only because so far it is the only one using adreno-smmu-priv. Signed-off-by:
Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210610214431.539029-6-robdclark@gmail.comSigned-off-by:
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Rob Clark authored
Add, via the adreno-smmu-priv interface, a way for the GPU to request the SMMU to stall translation on faults, and then later resume the translation, either retrying or terminating the current translation. This will be used on the GPU side to "freeze" the GPU while we snapshot useful state for devcoredump. Signed-off-by:
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Jordan Crouse authored
Use the new adreno-smmu-priv fault info function to get more SMMU debug registers and print the current TTBR0 to debug per-instance pagetables and figure out which GPU block generated the request. Signed-off-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
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Jordan Crouse authored
Add a callback in adreno-smmu-priv to read interesting SMMU registers to provide an opportunity for a richer debug experience in the GPU driver. Signed-off-by:
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Jordan Crouse authored
Call report_iommu_fault() to allow upper-level drivers to register their own fault handlers. Signed-off-by:
Will Deacon <will@kernel.org> Reviewed-by:
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Samuel Iglesias Gonsalvez authored
While keeping the previous default value for hangcheck period, we allow now the possibility of configuring its value via debugfs. Signed-off-by:
Samuel Iglesias Gonsalvez <siglesias@igalia.com> Link: https://lore.kernel.org/r/20210607104441.184700-1-siglesias@igalia.comSigned-off-by:
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Jonathan Marek authored
Add adreno_is_{a660,a650_family} helpers and convert update existing adreno_is_a650 usage based on downstream driver's logic (changing into adreno_is_a650_family or adding adreno_is_a660). And add the remaining changes required for A660, again based on the downstream driver: missing GMU allocations, additional register init, dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table, updated a6xx_ucode_check_version check. Signed-off-by:Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-6-jonathan@marek.caSigned-off-by:
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Jonathan Marek authored
See downstream's "disable_tseskip" flag. Signed-off-by:
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Jonathan Marek authored
downstream msm-5.14 kernel added a write to this register, so match that. Signed-off-by:
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Jonathan Marek authored
SM8250 AOP firmware already sets up PDC registers for us, and it only needs to be enabled. This path will be used for other newer GPUs. Signed-off-by:
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Jonathan Marek authored
These aren't used by anything anymore. Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210608172808.11803-2-jonathan@marek.caSigned-off-by:
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Rob Clark authored
Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5 Small bit of .c churn in the phy code to adapt to split up of phy related registers. Signed-off-by: -
Dmitry Baryshkov authored
The code does not really use dpu_hw_blk fields, so drop them, making dpu_hw_blk empty structure. Signed-off-by:
Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by:
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Dmitry Baryshkov authored
Use struct dpu_hw_merge_3d pointer in struct dpu_hw_pingpong rather than using struct dpu_hw_blk. This is the only user of dpu_hw_blk.id, which will be cleaned in the next patch. Signed-off-by:
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Dmitry Baryshkov authored
The dpu_hw_blk_destroy() function is empty, so we can drop it now. Signed-off-by:
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Dmitry Baryshkov authored
Remove all unused dpu_hw_blk features and functions: - dpu_hw_blk_get()/_put() and respective refcounting, - global list of all dpu_hw_blk instances, - dpu_hw_blk_ops and empty implementation inside each hw_blk subdriver. This leaves dpu_hw_blk as a placeholder with just type and index. Signed-off-by:
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