- 23 Feb, 2011 11 commits
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Stephen Warren authored
The ASoC machine driver was written assuming my previous patch to add complete support for these clocks, which named them cdev1/2. Rename the clocks to match that, to avoid churn in the ASoC driver. This rename also makes the clocks more consistent with other Tegra clocks irrespective of any of that. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Colin Cross <ccross@android.com>
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Stephen Warren authored
The driver is tegra-i2s not just i2s. Rename the clocks to match, so that clk_get_sys can look up by driver name. Signed-off-by:
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Stephen Warren authored
The following commit makes the Tegra APB DMA engine fail to initialize correctly: 0cf6230a ARM: tegra: Move tegra_common_init to tegra_init_early The reason is that tegra_init_early_ calls tegra_dma_init which calls request_threaded_irq, which fails since the IRQ hasn't yet been marked valid; that only happens in tegra_init_irq, which gets called after tegra_init_early. This used to work OK, since tegra_init_early was tegra_common_init, which got called after tegra_init_irq, basically from the beginning of tegra_harmony_init. Solve this by converting tegra_dma_init to a postcore_initcall. This makes it execute late enough that IRQs are marked valid, and avoids having to add it back to every machine's init function. Signed-off-by:
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Colin Cross authored
Merge branch 'boards-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra-2.6 into for-next
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Olof Johansson authored
This adds board support for the Seaboard eval platform and some of the derivatives that are very similar. Since they only differ in some very minor ways, most of the code is shared. Signed-off-by:
Olof Johansson <olof@lixom.net> Acked-by:
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Olof Johansson authored
Turns out MMC2 (the bayonet 4-lane port) wasn't enabled in the original pinmux. Fix that. Signed-off-by:
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Olof Johansson authored
Add the 3 sdhci devices that are available on Harmony as platform devices. Two go to slots (one 4-lane, one 8-lane), and one goes to onboard wifi. Signed-off-by:
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Olof Johansson authored
Remove dead atag handling code for nvidia-specific tags. Signed-off-by:
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Olof Johansson authored
Add a common location to register resources for used on-chip devices that are commonly configured on boards. Devices will be added to this file as more drivers are added that can make use of them. This is based on work contributed by several people, most of it from Colin Cross and Erik Gilling. Signed-off-by:
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Olof Johansson authored
Move harmony over to use the new gpio config table instead of having separate settings in various parts of the code. (The tegra sdhci driver should have the tegra_gpio_* ops removed, but that will be done separately from this change.) Signed-off-by:
Erik Gilling <konkers@android.com>
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Olof Johansson authored
To give one place to setup the pins that are used as GPIOs instead of as their pinmuxed functions. Specifying enabled as false explicitly disables the gpio mode of that pin (if left on by firmware). This should remove the need for calling these from specific drivers and thus reduce tegra-specific code from them. Signed-off-by:
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- 22 Feb, 2011 8 commits
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Mark Brown authored
The option isn't terribly useful on other ARM platforms. Signed-off-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by:
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Stephen Warren authored
Signed-off-by:
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Colin Cross authored
Enable the cpu, emc (memory controller) and csite (debug and trace controller) clocks during init to prevent them from being disabled by the bootloader clock disabling code. Signed-off-by:
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Colin Cross authored
Enable the timer and rtc clocks to prevent them being turned off by the bootloader clock disabling code. Signed-off-by:
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Colin Cross authored
Move tegra_common_init to tegra_init_early, and set it as the init_early entry in the machine struct. Initializes the clocks earlier so that timers can enable their clocks. Also reorders the members in the Harmony and Trimslice boards' machine structs to match the order they are called in. Signed-off-by:
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Colin Cross authored
Peripheral clocks that have no clock enable bit in the enable registers have their clk_num set to 0. Bit 0 in the clock enable registers is the CPU clock. Prevent disables on these peripheral clocks from accidentally disabling the CPU clock. Signed-off-by:
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Colin Cross authored
Call the clock's round_rate op, if it exists, before calling the set_rate op. This will help later when dvfs is added, dvfs needs to know what the final rate will be before the frequency changes. Also requires fixes to the round rate functions to ensure calling round rate and then set rate will not cause the frequency to be rounded down twice. When picking clock divider values, the clock framework picks the closest frequency that is lower than the requested frequency. If the new frequency calculated from the divider value is rounded down, and then passed to set_rate, it will get rounded down again, possibly resulting in a frequency two steps lower than the original requested frequency. Fix the problem by rounding up when calculating the frequency coming out of a clock divider, so if that frequency is requested again, the same divider value will be picked. Signed-off-by:
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Colin Cross authored
Some peripheral clocks share enable bits. Refcount the enables so that calling clk_disable on one clock will not turn off another clock. Signed-off-by:
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- 21 Feb, 2011 20 commits
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Colin Cross authored
Correct max rates for pclk and sclk (Originally fixed by Dima Zavin <dima@android.com>) Correct max rate for plla (Originally fixed by Stephen Warren <swarren@nvidia.com>) Remove unnecessary no-op set_rate on audio clocks Add clock lookup entries for grhost, bsea, and vde clocks Update clock clookup entries for vcp, bsea, and vde clocks Add shared clock entries for sclk and emc Add a virtual cop clock to provide a reset op (Originally fixed by Dima Zavin <dima@android.com>) Pass set_rate on super clocks through to parent Fix pllx frequency table entry for 608 MHz Remove incorrect plla frequency table entries Acked-by:
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Colin Cross authored
The PLLP registers are now being restored by the low-level resume code, and the CPU may be running off PLLP, so don't touch them during clock resume. Save plld, plls, pllu, and audio clock during suspend (originally fixed by Mayuresh Kulkarni <mkulkarni@nvidia.com>) The lock time for plld is 1000 us, so increase the delay after setting the PLLs. Add a BUG_ON to ensure the size of the suspend context area is correct. Acked-by:
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Colin Cross authored
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by:
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Colin Cross authored
Adjusts the minimum memory frequency when the cpu frequency changes. The values are currently hardcoded to a reasonable default. If memory frequency scaling is not enabled this patch will have no effect. Acked-by:
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Colin Cross authored
Add clock ops on the emc peripheral clock that call into the emc driver to update the memory controller registers for the new frequency. Tegra has an interlock between the clock controller and the memory controller that prevents the new register values from taking effect until the clock frequency update occurs. Acked-by:
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Colin Cross authored
The frequency memory bus on Tegra can be adjusted without disabling accesses to memory by updating the memory configuration registers from a per-board table, and then changing the clock frequency. The clock controller and memory controller have an interlock that prevents the new memory registers from taking effect until the clock frequency change. Acked-by:
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Colin Cross authored
Remove unnecessary uses of #ifdef CONFIG_DEBUG_FS Convert bool assignments from 1 to true Acked-by:
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Colin Cross authored
Some clocks may have multiple downstream users that need to request a higher clock rate. Shared bus clocks provide a unique shared_bus_user clock to each user. The frequency of the bus is set to the highest enabled shared_bus_user clock, with a minimum value set by the shared bus. Drivers can use clk_enable and clk_disable to enable or disable their requirement, and clk_set_rate to set the minimum rate. Acked-by:
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Colin Cross authored
During cpu frequency changes, take an extra reference to pllx so that it doesn't turn off and on while the cpu is temporarily on pllp. If the cpu is moved to pllp permanently, pllx will be turned off. Acked-by:
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Colin Cross authored
Give each clock its own lock, and remove all lock traversals from parent to child clocks to prevent AB-BA deadlocks. This brings the locking in line with the common struct clk patches and should make conversion simple. Acked-by:
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Colin Cross authored
Creates a union of a struct for each type of clock to reduce memory usage and clarify which members are used by all clocks and which are used by a single type. Acked-by:
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Colin Cross authored
Make the static clocks look more like the array of clocks so they can all be initalized with the same helper function. Acked-by:
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Colin Cross authored
The existing version did not extend well to core dvfs, drop it for now until the new clk api with clk_prepare and clk_unprepare is ready and non-atomic clocks are possible. Acked-by:
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Colin Cross authored
Assume that any clock that has no enable op is always on. Acked-by:
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Colin Cross authored
The PLL lock bits are not reliable, use per-PLL timeouts instead. Acked-by:
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Colin Cross authored
Drop the unnecessary pr_debug calls to avoid having to maintain them. Acked-by:
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Colin Cross authored
When updating the CPU PLL frequency, keeping the PLL enabled avoids ramping the PLL all the way down and back up again. Remove the BUG_ON in tegra2_pll_clk_set_rate to allow the rate to change while the PLL is enabled. Acked-by:
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Dima Zavin authored
Add a new 'reset' clk op. This can be provided for any clock, not just peripherals. Signed-off-by:
Dima Zavin <dima@android.com> Acked-by:
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Simon Glass authored
This seems to be a regression in 2.6.37. We cannot use writel() here since the resulting wmb() calls l2x0_cache_sync() which uses a spinlock and L1 cache may be off at this point. http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041909.htmlSigned-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
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Stephen Warren authored
Signed-off-by:
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- 19 Feb, 2011 1 commit
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Stephen Warren authored
If a request already in the queue is passed to tegra_dma_enqueue_req, tegra_dma_req.node->{next,prev} will end up pointing to itself instead of at tegra_dma_channel.list, which is the way a the end-of-list should be set up. When the DMA request completes and is list_del'd, the list head will still point at it, yet the node's next/prev will contain the list poison values. When the next DMA request completes, a kernel panic will occur when those poison values are dereferenced. This makes the DMA driver more robust in the face of buggy clients. Signed-off-by:
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