- 07 May, 2013 40 commits
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Gabor Juhos authored
Add cpu-feature-overrides.h for RT288x, RT305x and RT3883. Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5175/
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John Crispin authored
Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by:
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John Crispin authored
Add support code for rt3883 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by:
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John Crispin authored
Add support code for rt2880 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by:
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John Crispin authored
Add a field for the uart muxing mask and set it inside the rt305x setup code. Signed-off-by:
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Gabor Juhos authored
This will be used for RT3662/RT3883. Signed-off-by:
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John Crispin authored
These structures are exported via struct ralink_pinmux rt_gpio_pinmux and can hence be static. Signed-off-by:
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John Crispin authored
Add proper namespacing to the variable. Signed-off-by:
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John Crispin authored
RT2880 has a different location for the early serial port. Signed-off-by:
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John Crispin authored
Add a few missing defines that are needed to make memory detection work on the RT5350. Signed-off-by:
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John Crispin authored
Trivial patch that adds a comment that makes the code more readable. Signed-off-by:
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John Crispin authored
Add a few missing clocks. Signed-off-by:
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John Crispin authored
Add a few missing defines that are needed to make USB and clock detection work on the RT3352. Signed-off-by:
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Gabor Juhos authored
The Ralink IRQ code was not handling the PCI IRQ yet. Add this functionaility to make PCI work on rt3883. Signed-off-by:
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John Crispin authored
Previously this functionality was only available to users of the mips_machine api. Moving the code to prom.c allows us to also add a OF wrapper. Signed-off-by:
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Alexander Sverdlin authored
Current GPIO chip implementation in octeon-irq is still broken, even after upstream commit 87161ccd (MIPS: Octeon: Fix broken interrupt controller code). It works for GPIO IRQs that have reset-default configuration, but not for edge-triggered ones. The problem is in octeon_irq_gpio_map_common(), which passes modified "hw" variable (which has range of possible values 16..31) as "gpio_line" parameter to octeon_irq_set_ciu_mapping(), which saves it in private data of the IRQ chip. Later, neither octeon_irq_gpio_setup() is able to re-configure GPIOs (cvmx_write_csr() is writing to non-existent CVMX_GPIO_BIT_CFGX), nor octeon_irq_ciu_gpio_ack() is able to acknowledge such IRQ, because "mask" is incorrect. Fix is trivial and has been tested on Cavium Octeon II -based board, including both level-triggered and edge-triggered GPIO IRQs. Signed-off-by:
Alexander Sverdlin <alexander.sverdlin.ext@nsn.com> Cc: David Daney <david.daney@cavium.com> Acked-by:
David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4980/Acked-by:
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Silviu-Mihai Popescu authored
Convert all uses of devm_request_and_ioremap() to the newly introduced devm_ioremap_resource() which provides more consistent error handling. Signed-off-by:
Silviu-Mihai Popescu <silviupopescu1990@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4986/Acked-by:
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David Daney authored
The operations on the bitmap pointers are protected by "memory" clobbering raw_local_irq_{save,restore}(), so there is no need for volatile here. By removing the volatile we get better code generation out of the compiler. Signed-off-by: -
Huacai Chen authored
Currently, init_new_context() only for each online CPU, this may cause memory corruption when CPU hotplug and fork() happens at the same time. To avoid this, we make init_new_context() cover each possible CPU. Scenario: 1, CPU#1 is being offline; 2, On CPU#0, do_fork() call dup_mm() and copy a mm_struct to the child; 3, On CPU#0, dup_mm() call init_new_context(), since CPU#1 is offline and init_new_context() only covers the online CPUs, child has the same asid as its parent on CPU#1 (however, child's asid should be 0); 4, CPU#1 is being online; 5, Now, if both parent and child run on CPU#1, memory corruption (e.g. segfault, bus error, etc.) will occur. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Acked-by:
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Huacai Chen authored
This and the next patch resolve memory corruption problems while CPU hotplug. Without these patches, memory corruption can triggered easily as below: On a quad-core MIPS platform, use "spawn" of UnixBench-5.1.3 (http:// code.google.com/p/byte-unixbench/) and a CPU hotplug script like this (hotplug.sh): while true; do echo 0 >/sys/devices/system/cpu/cpu1/online echo 0 >/sys/devices/system/cpu/cpu2/online echo 0 >/sys/devices/system/cpu/cpu3/online sleep 1 echo 1 >/sys/devices/system/cpu/cpu1/online echo 1 >/sys/devices/system/cpu/cpu2/online echo 1 >/sys/devices/system/cpu/cpu3/online sleep 1 done Run "hotplug.sh" and then run "spawn 10000", spawn will get segfault after a few minutes. This patch: Currently, clear_page()/copy_page() are generated by Micro-assembler dynamically. But they are unavailable until uasm_resolve_relocs() has finished because jump labels are illegal before that. Since these functions are shared by every CPU, we only call build_clear_page()/ build_copy_page() only once at boot time. Without this patch, programs will get random memory corruption (segmentation fault, bus error, etc.) while CPU Hotplug (e.g. one CPU is using clear_page() while another is generating it in cpu_cache_init()). For similar reasons we modify build_tlb_refill_handler()'s invocation. V2: 1, Rework the code to make CPU#0 can be online/offline. 2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU need a per-CPU tlb_refill_handler(). Signed-off-by:
Hongbing Hu <huhb@lemote.com> Acked-by:
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Paul Bolle authored
The Kconfig symbol MIPS_DISABLE_OBSOLETE_IDE was added in v2.6.10. It has never been used. Let's remove it. The symbol was originally introduced by the following commit commit 2bfa662b64a7ee593f3039c1d3fd81a7766a63cd Author: Pete Popov <ppopov@embeddedalley.com> Date: Tue Oct 12 06:24:19 2004 +0000 - Db1550 bug fixes - updated defconfig - updated Kconfig to use DMA_COHERENT since new silicon is coherent Signed-off-by:Paul Bolle <pebolle@tiscali.nl> Patchwork: http://patchwork.linux-mips.org/patch/5064/Acked-by:
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Paul Bolle authored
The Kconfig symbol MIPS_BOARDS_GEN is unused since v2.6.27. It should now be removed. Signed-off-by:
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Paul Bolle authored
The support for PB1100, PB1500, and PB1550 got merged into the code for DB1000 and DB1550 code in v3.7. When that was done the three related Kconfig symbols were dropped. But not all related Kconfig macros were removed. Do so now. Note that the PB1100 code in the Au1100 LCD driver is removed entirely and not converted to use its current Kconfig macro. That is done because the macros it uses (PB1100_G_CONTROL, PB1100_G_CONTROL_BL, and PB1100_G_CONTROL_VDD) are never defined. Actually only one of these was ever defined (PB1100_G_CONTROL) but that define was removed in v2.6.34. So, as far as I can tell, this code could have never compiled. Signed-off-by:
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Jayachandran C authored
The commit c783390a [MIPS: oprofile: Support for XLR/XLS processors] causes a compilation failure when oprofile is enabled and SMP is not configured. arch/mips/oprofile/op_model_mipsxx.c: In function 'mipsxx_cpu_setup': arch/mips/oprofile/op_model_mipsxx.c:181:2: error: implicit declaration of function 'cpu_logical_map' To fix this, update oprofile_skip_cpu to not call cpu_logical_map when CONFIG_SMP is not defined. Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5037/Acked-by:
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Jayachandran C authored
The definitions are not used anywhere else, and merging it will make adding the new USB definitions for XLPII series easier. While there, cleanup some whitespace in usb-init.c. There is no change to logic due to this commit. Signed-off-by:
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Jayachandran C authored
This enables us to have a default device tree per SoC family to be built into the kernel. The default device tree for XLP3xx has been added as part of this change. Later this can be used to provide support default boards for XLP2xx and XLP9xx SoCs. Kconfig options are provided for each default device tree so that just the needed ones can be selected to be built into the kernel. Signed-off-by:
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Jayachandran C authored
Remove unused functions and redundant comments from arch/mips/include/asm/netlogic/haldefs.h Signed-off-by:
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Jayachandran C authored
Update asm/netlogic/haldefs.h to extend register access functions nlm_{read,write}_reg64() for 32-bit compilation. When compiled for 32-bit the functions will read 64 IO registers with interrupts disabled. Signed-off-by: -
Jayachandran C authored
The index for a device interrupt in the PIC interrupt routing table changes for different chips in the XLP family. Avoid using the fixed entries and derive the index value from the SoC device header. Add workarounds for some devices which do not report the IRT index correctly. Signed-off-by:
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Jayachandran C authored
Use standard function to print cpumask. Also fixup the name of the variable used and make it static. Signed-off-by:
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Jayachandran C authored
Remove the definitions of {read,write}_c0_{eirr,eimr}. These functions are now unused after the PIC and IRQ code has been updated to use optimized EIMR/EIRR functions which work on both 32-bit and 64-bit. Signed-off-by: -
Jayachandran C authored
Remove the irq save/restore from write_c0_eimr(), as it is always called with interrupts off. This allows us to remove workaround in write_c0_eimr() to fix up the flags used by local_irq_save. This fixup worked on XLR, but will break when 32-bit support is added to r2 cpus like XLP. Signed-off-by:
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Jonas Gorski authored
All the header file does is provide the internal structure of clk, which shouldn't be used by anyone except clk.c itself anyway. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Patchwork: http://patchwork.linux-mips.org/patch/5055/Acked-by:
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Jonas Gorski authored
BCM6362 support booting from SPI flash and NAND. Signed-off-by:
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Jonas Gorski authored
The PCIe controller is almost the same as the BCM6328 one, with only the SERDES register being at a different location. Signed-off-by:
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Jonas Gorski authored
The SPI controller shares the same register layout as the 6358 one. Signed-off-by:
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Jonas Gorski authored
Add basic support for detecting and booting the BCM6362. Signed-off-by:
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Jonas Gorski authored
Instead of trying to use a correlation of cpu prid and chip id and hoping they will always be unique, use the cpu prid to determine the chip id register location and just read out the chip id. Signed-off-by:
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Jonas Gorski authored
The REVID is only 8 bit wide. Signed-off-by:
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Jonas Gorski authored
BCM6338 and BCM6348, and BCM6358 and everything after that share the same register layout. To not have to redefine them for each new chip and keep the code size small, only use the definitions for the first chip with the certain layout. Signed-off-by:
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