- 24 May, 2018 2 commits
-
-
Linus Walleij authored
Merge tag 'samsung-pinctrl-4.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v4.18 1. Driver expects specific order of GPIO interrupt banks. For S5Pv220 and Exynos5410 this order was not preserved so fix and document it. 2. Remove support for Exynos5440 (tree-wide, support is dropped because there are no real users of this platform, it also did not get testing since long time). 3. Fix lost state of GPF1..5 pins on Exynos5433 during system suspend.
-
Linus Walleij authored
Merge tag 'sh-pfc-for-v4.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.18 (take two) - Add support for the new R-Car E3 SoC, - Add I2C pin groups on R-Car M3-N, - Small fixes and cleanups.
-
- 23 May, 2018 17 commits
-
-
Marek Szyprowski authored
GPF1..5 banks in Exynos5433 are located in two pinctrl devices: ALIVE and IMEM. Although they are partially located in ALIVE section, the state of their registers in IMEM section is lost after suspend/resume cycle. To properly handle such case, those banks have to be defined with standard 'exynos5433_bank_type_off' type (with PINCFG_TYPE_CON_PDN and PINCFG_TYPE_PUD_PDN register offsets). This automatically instructs the generic Samsung pinctrl suspend/resume code to save and restore state of those registers. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org>
-
Geert Uytterhoeven authored
The comment block explaining the rationale for static pins contains grammar errors. It appeared first in the pin control driver for R-Car H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later. Fix the grammar in all copies at once. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
-
Niklas Söderlund authored
Signed-off-by:
-
Takeshi Kihara authored
This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP pins for the R8A77990 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
-
Takeshi Kihara authored
This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to the R8A77990 SoC. NOTE: I2C0 and I2C3 are not pin multiplexed. Signed-off-by: -
Takeshi Kihara authored
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch implements control of pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by:
-
Takeshi Kihara authored
This patch adds initial pinctrl driver to support for the R8A77990 SoC. Signed-off-by:
-
Takeshi Kihara authored
This follows the style of existion PORT_GP_X macros and will be used by a follow-up patch for the r8a77990 SoC. Signed-off-by:
-
Jisheng Zhang authored
Use the appropriate SPDX license identifier in the berlin pinctrl driver source file and drop the previous license text. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Shawn Lin authored
Could only support PIN_CONFIG_INPUT_DEBOUNCE now as the HW block is too simple to support others. But even wrt. debounce capability, it now could only support very limited period of time to satisfy the real usecase. But still be useful to enable the crippled HW debounce to prevent any spurious glitches from waking up the system if the gpio is conguired as wakeup interrupt source. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
-
David Wu authored
There are 4 banks (GPIO0 ~ GPIO3), bank0 is in PD_PMU subsystem, bank1/bank2/bank3 are in PD_BUS subsystem. Signed-off-by:
David Wu <david.wu@rock-chips.com> Reviewed-by:
-
Chris Packham authored
The Armada 98dx3236 SoCs don't have a different MPP sel value for nand specific pins so "dev" was technically correct. But all the other Armada SoCs use "nand" in their dts and the pin is specific to the nand interface so use "nand" for the function name. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
-
Manivannan Sadhasivam authored
Add S900 pinctrl entries under ARCH_ACTIONS Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
-
Manivannan Sadhasivam authored
Add gpio support to pinctrl driver for Actions Semi S900 SoC. Signed-off-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
-
Manivannan Sadhasivam authored
Add gpio bindings for Actions Semi S900 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Keerthy authored
This adds a pair of context save/restore functions to save/restore the state of a set of pinctrl registers. The context is lost during rtc only suspend with ddr in self-refresh on am43xx. Currently the save/restore is being done unconditionally. This will be optimized later with a pdata-quirk function which will allow is to save/restore only when doing the rtc only mode with ddr in self refresh. Signed-off-by:
Keerthy <j-keerthy@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
-
- 16 May, 2018 21 commits
-
-
Yixun Lan authored
The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: 0f15f500 ("pinctrl: meson: Add GXL pinctrl definitions") Reported-by:
Liang Yang <liang.yang@amlogic.com> Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
-
Yixun Lan authored
The data pin 0-7 of the NAND controller are actually missing from the nand pinctrl group, so we fix it here. Fixes: cd1e3b01 ("pinctrl: amlogic: gxbb: add nand pins") Reported-by:
-
Stephen Boyd authored
I was debugging some gpio issues and I thought that the output of gpio debugfs was telling me the high or low level of the gpios with a '1' or a '0'. We saw a line like this though: gpio93 : in 4 2mA pull down and I started to think that there may be a gas leak in the building because '4' doesn't mean high or low, and other pins said '0' or '1'. It turns out, '4' is the function selection for the pinmux of the gpio and not the value on the pin. Reading code helps decipher what debugfs is actually saying. Add support to read the input or output pin depending on how the pin is configured so we can easily see the high or low value of the pin in debugfs. Now the output looks like gpio93 : in low func4 2mA pull down which clearly shows that the pin is an input, low, with function 4 and a 2mA drive strength plus a pull down. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Alexandru M Stan <amstan@chromium.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
-
Chris Packham authored
The "dev" function is selected with the value 0x4 not 0x01. Fixes: commit d7ae8f8d ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC") Signed-off-by:
-
Clément Péron authored
DebugFS strings about pin pull status for no_keeper SoC are wrong Fix this by adding a different string array for no_keeper SoC Signed-off-by:
Clément Péron <peron.clem@gmail.com> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
-
Dmitry Osipenko authored
Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Reviewed-by:
Marcel Ziswiler <marcel@ziswiler.com> Tested-by:
Marc Dietrich <marvin24@gmx.de> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
-
Icenowy Zheng authored
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs, which controls the PL and PM pin banks. Add support for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Acked-by:
-
Andy Shevchenko authored
The new helper returns index of the matching string in an array. We are going to use it here. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
-
Matheus Castello authored
Properties to set initial value of pin output buffer. This can be useful for configure hardware in overlay files, and in early boot for checking it states in QA sanity tests. Signed-off-by:
Matheus Castello <matheus@castello.eng.br> Reviewed-by:
Eric Anholt <eric@anholt.net> Acked-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
-
Matheus Castello authored
To keep driver up to date we add generic pinctrl binding support, which covers the features used in this driver and has additional node properties that this SoC has compatibility, so enabling future implementations of these properties without the need to create new node properties in the device trees. The logic of this change maintain the old brcm legacy binding support in order to keep the ABI stable. Signed-off-by:
-
Biju Das authored
Add PFC support for the R8A77470 SoC including pin groups for some on-chip devices such as SCIF and MMC. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by:
-
Takeshi Kihara authored
This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by:Yoshihiro Kaneko <ykaneko0929@gmail.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Tested-by:
-
Kieran Bingham authored
This patch adds pins, groups and functions for parallel RGB output signals from DU. The HDMI and TCON pins are added to separate groups. Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
-
Thomas Gleixner authored
GPL-2. is not a valid SPDX identifier. Make it GPL-2.0 Fixes: 490e687e ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Rob Herring <robh@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
-
Sergei Shtylyov authored
I've included the pin I/O voltage control into the R8A77970 PFC driver but it was incomplete because: - SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly; - sh_pfc_soc_info::ioctrl_regs wasn't set at all... Fixes: b92ac66a ("pinctrl: sh-pfc: Add R8A77970 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
-
Sergei Shtylyov authored
Add the pin I/O voltage level control support to the R8A77980 PFC driver. Loosely based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
-
Biju Das authored
Document PFC support for the R8A77470 SoC. Signed-off-by:
-
Takeshi Kihara authored
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to R8A77965 SoC. Signed-off-by: -
Geert Uytterhoeven authored
Signed-off-by:
-
Geert Uytterhoeven authored
Signed-off-by:
-
Takeshi Kihara authored
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by:
-
