- 18 Jun, 2018 18 commits
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Dhinakaran Pandiyan authored
The Graphics System Event(GSE) interrupt bit has a new location in the GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only DE_MISC interrupt that was enabled, with this change we don't enable/handle any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out the register change. v2: from DK raw_reg_[read/write], branch prediction hint and drop platform check (Mika) v3: From DK Early re-enable of master interrupt (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> [Paulo: bikesheds and rebases] Signed-off-by:
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Paulo Zanoni authored
While I don't see any issue with the way these macros are being called today, let's protect them against operator precedence issues before they happen. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Paulo Zanoni authored
Since I'm touching the file I might as well fix this class of errors since they are just a few. Also drive-by fix the styling of the VLV_TURBO_SOC_OVERRIDE definitions instead of just the spaces before the tabs. Reviewed-by:
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Paulo Zanoni authored
Because OCD. Now seriously, commit 1aa920ea ("drm/i915: add register macro definition style guide") has finally established a coding standard to be followed by the rest of the file, and I've been trying to request everybody to adhere to that since then. The problem is that when someone adds a new line to a register that has the wrong style, these people generally propagate the wrong style and I have to keep asking them to drive-by fix the whole register, which is not something I like to do and also creates extra work for them. Or I can ignore the propagation of the wrong coding style and feel anxious about it. On top of that, we now have our CI happily reminding us about these problems, which makes everything worse. So IMHO the best way to proceed is to fix the spacing issues in the file once and for all. Contributors will stop propagating the bad style when adding new bits to registers that already have bad style, we will stop asking them to redo their patches and the CI emails will become more relevant by having less semi-false errors. Yes, there will be some pain involved for backporters, but at least spacing issues like that are easy to spot and fix in the patch files. This patch was generated by: ../../../../scripts/checkpatch.pl -f --strict --types SPACING \ --fix-inplace i915_reg.h I manually checked the output and everything seems sane. v2: Single conflict around the addition of DP_TP_CTL_LINK_TRAIN_PAT4. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
Expand the Maud/Naud table according to DP 1.4 spec to include entries for 810 MHz clock. This is required for audio to work with HBR3. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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José Roberto de Souza authored
Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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José Roberto de Souza authored
Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. So, let's just move them to WHL macros that will feed into CFL macro just to keep it better organized to make easier future code review but it will be handled as a CFL. v2: Fixing GT level of some ids Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Chris Wilson authored
Having the w/a registers as an open-coded table leaves a trap for the unwary; it would be easy to miss incrementing the LRI counter when adding a new register to the list. Instead, pull the list of registers into a table, so that we only need add new registers to that table rather than try and remember important side-effects of earlier chunks of GPU instructions. Suggested-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
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Chris Wilson authored
Since we trigger 10,000s of hangs and resets during selftesting, we emit many, many thousands of lines of useless debug messages. Reduce the frequency by only logging a change in state of a guilty context. Fixes: 14921f3c ("drm/i915: Fix context ban and hang accounting for client") Signed-off-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. v2: fix checkpatch warning on indentation Reviewed-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by:
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Jani Nikula authored
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try to stick to kernel types at least where it's more prevalent. Reviewed-by:
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Chris Wilson authored
commit b2209e62 ("drm/i915/execlists: Reset the CSB head tracking on reset/sanitization") and commit 1288786b ("drm/i915: Move GEM sanitize from resume_early to resume") show the conflicting requirements on the code. We must reset the GPU before trashing live state on a fast resume (hibernation debug, or error paths), but we must only reset our state tracking iff the GPU is reset (or power cycled). This is tricky if we are disabling GPU reset to simulate broken hardware; we reset our state tracking but the GPU is left intact and recovers from its stale state. v2: Again without the assertion for forcewake, no longer required since commit b3ee09a4 ("drm/i915/ringbuffer: Fix context restore upon reset") as the contexts are reset from the CS ensuring everything is powered up. Fixes: b2209e62 ("drm/i915/execlists: Reset the CSB head tracking on reset/sanitization") Fixes: 1288786b ("drm/i915: Move GEM sanitize from resume_early to resume") Signed-off-by:
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Kenneth Graunke authored
The SF and clipper units mishandle the provoking vertex in some cases, which can cause misrendering with shaders that use flat shaded inputs. There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN (for the clipper) that work around the issue. These registers are unfortunately not part of the logical context (even the power context), and so we must reload them every time we start executing in a context. Bugzilla: https://bugs.freedesktop.org/103047Signed-off-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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- 15 Jun, 2018 7 commits
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Paulo Zanoni authored
Some bits from the flags2 field are going to be used in the next patches, so replace the whole-byte definition with the actual bits and document their versions. This patch is based on a patch by Animesh Manna. Cc: Animesh Manna <animesh.manna@intel.com> Credits-to: Animesh Manna <animesh.manna@intel.com> Reviewed-by:
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Paulo Zanoni authored
ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK table. Implement it just like CNL does. References: commit 48469ece ("drm/i915: Use cdclk_state->voltage on CNL") References: commit 53e9bf5e ("drm/i915: Adjust system agent voltage on CNL if required by DDI ports") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Ville Syrjälä authored
We have IS_G45 these days. Let's use it instead of the 'IS_G4X && !IS_GM45' construct. Signed-off-by:
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Chris Wilson authored
We can avoid the mmio read of the CSB pointers after reset based on the knowledge that the HW always start writing at entry 0 in the CSB buffer. We need to reset our CSB head tracking after GPU reset (and on sanitization after resume) so that we are expecting to read from entry 0, hence we reset our head tracking back to the entry before (the last entry in the ring). Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615093137.14270-2-chris@chris-wilson.co.uk
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Chris Wilson authored
As we want to be able to call i915_reset_engine and co from a softirq or timer context, we need to be irqsafe at all times. So we have to forgo the simple spin_lock_irq for the full spin_lock_irqsave. Signed-off-by:
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Mika Kuoppala authored
If client is smart or lucky enough to create a new context after each hang, our context banning mechanism will never catch up, and as a result of that it will be saved from client banning. This can result in a never ending streak of gpu hangs caused by bad or malicious client, preventing access from other legit gpu clients. Fix this by always incrementing per client ban score if it hangs in short successions regardless of context ban scoring. The exception are non bannable contexts. They remain detached from client ban scoring mechanism. v2: xchg timestamp, tidyup (Chris) v3: comment, bannable & banned together (Chris) Fixes: b083a087 ("drm/i915: Add per client max context ban limit") Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
For each platform, we have a few registers that are rewritten with different values -- they are not part of a sequence, just different parts of a masked register set at different times (e.g. platform and gen workarounds). Consolidate these into a single register write to keep the table compact, important since we are running of room in the current fixed sized buffer. While adjusting the construction of the wa table, make it non fatal so that the driver still loads but keeping the warning and extra details for inspection. Inspecting the changes for a Kabylake system, Before: Address val mask read 0x07014 0x20002000 0x00002000 0x00002100 0x0E194 0x01000100 0x00000100 0x00000114 0x0E4F0 0x81008100 0x00008100 0xFFFF8120 0x0E184 0x00200020 0x00000020 0x00000022 0x0E194 0x00140014 0x00000014 0x00000114 0x07004 0x00420042 0x00000042 0x000029C2 0x0E188 0x00080000 0x00000008 0x00008030 0x07300 0x80208020 0x00008020 0x00008830 0x07300 0x00100010 0x00000010 0x00008830 0x0E184 0x00020002 0x00000002 0x00000022 0x0E180 0x20002000 0x00002000 0x00002000 0x02580 0x00010000 0x00000001 0x00000004 0x02580 0x00060004 0x00000006 0x00000004 0x07014 0x01000100 0x00000100 0x00002100 0x0E100 0x00100010 0x00000010 0x00008050 After: Address val mask read 0x02580 0x00070004 0x00000007 0x00000004 0x07004 0x00420042 0x00000042 0x000029C2 0x07014 0x21002100 0x00002100 0x00002100 0x07300 0x80308030 0x00008030 0x00008830 0x0E100 0x00100010 0x00000010 0x00008050 0x0E180 0x20002000 0x00002000 0x00002000 0x0E184 0x00220022 0x00000022 0x00000022 0x0E188 0x00080000 0x00000008 0x00008030 0x0E194 0x01140114 0x00000114 0x00000114 0x0E4F0 0x81008100 0x00008100 0xFFFF8120 Signed-off-by:
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- 14 Jun, 2018 15 commits
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Manasi Navare authored
DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link rate. This will be used in link training's channel equalization phase if supported by both source and sink. This patch adds the helpers to check if HBR3 is supported and uses TPS4 in training pattern selection during link training. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by:
James Ausmus <james.ausmus@intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Manasi Navare authored
For ICL, on Combo PHY the allowed max rates are: - HBR3 8.1 eDP (DDIA) - HBR2 5.4 DisplayPort (DDIB) and for MG PHY/TC DDI Ports allowed DP rates are: - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT, - DP on legacy connector - DDIC/D/E/F) v2 (from Paulo): Remove misleading comment (Ville). Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by:
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Paulo Zanoni authored
This commit just adds the register addresses and the basic skeleton of the code. The next commits will expand on more specific functions. Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Paulo Zanoni authored
On ICP, port present straps (from SFUSE_STRAP PCH register) are no longer supported. Software should determine the presence through BIOS VBT, hotplug or other mechanisms. v2: Improve commit message (Lucas). Reviewed-by:
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Paulo Zanoni authored
Implement the hardware state readout code. Thanks to Animesh Manna for spotting this problem. Cc: Animesh Manna <animesh.manna@intel.com> Credits-to: Animesh Manna <animesh.manna@intel.com> Reviewed-by:
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Chris Wilson authored
We can stop asserting using WARN_ON as given sufficient CI coverage, we can rely on using GEM_BUG_ON() to catch problems before merging. Signed-off-by:
Matthew Auld <matthew.william.auld@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180614184218.1606-2-chris@chris-wilson.co.uk
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Chris Wilson authored
As the most frequent PTE encoding is for the scratch page, cache it upon creation. Signed-off-by:
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Chris Wilson authored
As we cannot reliably change used page tables while the context is active, the earliest opportunity we have to recover excess pages is when the context becomes idle. So whenever we unbind the context (it must be idle, and indeed being evicted) free the unused ptes. Signed-off-by:
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Chris Wilson authored
As we were only supporting aliasing_ppgtt on gen7 for some time, we saved a few checks by preallocating the page directories on creation. However, since we need 2MiB of page directories for each ppgtt, to support arbitrary numbers of user contexts, we need to be more prudent in our allocations, and defer the page allocation until it is used. We don't recover unused pages yet as we found that doing so on the fly (i.e. altering TLB entries) would confuse the GPU. Signed-off-by:
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Chris Wilson authored
Hangcheck is our back up in case the GPU or the driver gets stuck. It detects when the GPU is not making any progress and issues a GPU reset. However, if the driver is failing to make any progress, we can get ourselves into a situation where we continually try resetting the GPU to no avail. Employ a second timeout such that if we continue to see the same seqno (the stalled engine has made no progress at all) over the course of several hangchecks, declare the driver wedged and attempt to start afresh. Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com>
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Chris Wilson authored
In the unlikely case where we have failed to keep submitting to the GPU, we end up with the ELSP queue empty but a pending queue of requests. Here, we skip the per-engine reset as there is no guilty request, but in doing so we also skip the engine restart leaving ourselves with a permanently hung engine. A quick way to recover is by moving the tasklet kick to execlists_reset_finish() (from init_hw). We still emit the error on hanging, so the error is not lost but we should be able to recover. Signed-off-by:
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Chris Wilson authored
With an old (4.7.3 on 32bit) gcc, it emits a warning for In file included from drivers/gpu/drm/i915/i915_request.c:1425:0: drivers/gpu/drm/i915/selftests/i915_request.c: In function ‘live_nop_request’: drivers/gpu/drm/i915/selftests/i915_request.c:380:21: error: ‘request’ may be used uninitialized in this function [-Werror=maybe-uninitialized] Silence it by just setting it to NULL on initialisation. Signed-off-by:
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Ville Syrjälä authored
While Bspec doesn't list a specific sequence for turning off the DP port on g4x we are getting an underrun if the port is disabled in the .disable() hook. Looks like the pipe stops when the port stops, and by that time the plane disable may not have completed yet. Also the plane(s) seem to end up in some wonky state when this happens as they also signal another underrun immediately after we turn them back on during the next enable sequence. We could add a vblank wait in .disable() to avoid wedging the planes, but I assume we're still tripping up the pipe in some way. So it seems better to me to just follow the ILK+ sequence and turn off the DP port in .post_disable() instead. This sequence doesn't seem to suffer from this problem. Could be it was always the intended sequence for DP and the gen4 bspec was just never updated to include it. Originally we used the bad sequence even on ilk+, but I changed that in commit 08aff3fe ("drm/i915: Move DP port disable to post_disable for pch platforms") as it was causing issues on those platforms as well. I left out g4x then only because I didn't have the hardware to test it. Now that I do it's fairly clear that the ilk+ sequence is also the right choice for g4x. v2: Fix whitespace fail (Jani) Mention the ilk+ commit (Jani) Cc: stable@vger.kernel.org Signed-off-by:
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Ville Syrjälä authored
Looks like interlaced DP output doesn't work on g4x either. Not all that surprising considering we already established that interlaced DP output is busted on VLV/CHV. Cc: stable@vger.kernel.org Signed-off-by:
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Ville Syrjälä authored
On i965/g4x IIR is edge triggered. So in order for IIR to notice that there is still a pending interrupt we have to force and edge in ISR. For the ISR/IIR pipe event bits we can do that by temporarily clearing all the PIPESTAT enable bits when we ack the status bits. This will force the ISR pipe event bit low, and it can then go back high when we restore the PIPESTAT enable bits. This avoids the following race: 1. stat = read(PIPESTAT) 2. an enabled PIPESTAT status bit goes high 3. write(PIPESTAT, enable|stat); 4. write(IIR, PIPE_EVENT) The end result is IIR==0 and ISR!=0. This can lead to nasty vblank wait/flip_done timeouts if another interrupt source doesn't trick us into looking at the PIPESTAT status bits despite the IIR PIPE_EVENT bit being low. Before i965 IIR was level triggered so this problem can't actually happen there. And curiously VLV/CHV went back to the level triggered scheme as well. But for simplicity we'll use the same i965/g4x compatible code for all platforms. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030Signed-off-by:
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