- 20 Feb, 2013 1 commit
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Benjamin Herrenschmidt authored
<< Please pull mpc5xxx patches for v3.9. The bestcomm driver is moved to drivers/dma (so it will be usable for ColdFire). mpc5121 now provides common dtsi file and existing mpc5121 device trees use it. There are some minor clock init and sparse fixes and updates for various 5200 device tree files from Grant. Some fixes for bugs in the mpc5121 DIU driver are also included here (Andrew Morton suggested to push them via my mpc5xxx tree). >>
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- 19 Feb, 2013 3 commits
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Benjamin Herrenschmidt authored
<< Mostly misc code cleanups in various board ports and adding support for a new MPC85xx board - ppa8548. >>
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Harninder Rai authored
Signed-off-by:
Harninder Rai <harninder.rai@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Harninder Rai authored
BSC9131RDB doesn't have SDHC enabled. As a result of this typo, the node was not getting disabled from the device tree which was leading to linux hang during bootup Signed-off-by:
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- 15 Feb, 2013 32 commits
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Scott Wood authored
The MPIC code will disable coreint if it detects an insufficient MPIC version. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Scott Wood authored
This will be used by the qemu-e500 platform, as the MPIC version (and thus whether we have coreint) depends on how QEMU is configured. Signed-off-by:
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Varun Sethi authored
The pci controller structure has a provision to store the device structure pointer of the corresponding platform device. Currently this information is not stored during fsl pci controller initialization. This information is required while dealing with iommu groups for pci devices connected to the fsl pci controller. For the case where the pci devices can't be paritioned, they would fall under the same device group as the pci controller. This patch stores the platform device information in the pci controller structure during initialization. Signed-off-by:
Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by:
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Stef van Os authored
Initial board support for the Prodrive PPA8548 AMC module. Board is an MPC8548 AMC platform used in RapidIO systems. This module is also used to test/work on mainline linux RapidIO software. PPA8548 overview: - 1.3 GHz Freescale PowerQUICC III MPC8548 processor - 1 GB DDR2 @ 266 MHz - 8 MB NOR flash - Serial RapidIO 1.2 - 1 x 10/100/1000 BASE-T front ethernet - 1 x 1000 BASE-BX ethernet on AMC connector Signed-off-by:
Stef van Os <stef.van.os@prodrive.nl> Acked-by:
Timur Tabi <timur@tabi.org> Signed-off-by:
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Timur Tabi authored
The Freescale DIU driver was recently updated to not require every DIU platform function, so now we can remove the unneeded functions from some boards. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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Julia Lawall authored
Delete successive tests to the same location. The code tested the result of a previous call, that itself was already tested. It is changed to test the result of the most recent call. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @s exists@ local idexpression y; expression x,e; @@ *if ( \(x == NULL\|IS_ERR(x)\|y != 0\) ) { ... when forall return ...; } ... when != \(y = e\|y += e\|y -= e\|y |= e\|y &= e\|y++\|y--\|&y\) when != \(XT_GETPAGE(...,y)\|WMI_CMD_BUF(...)\) *if ( \(x == NULL\|IS_ERR(x)\|y != 0\) ) { ... when forall return ...; } // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Michael Neuling authored
Signed-off-by:
Matt Evans <matt@ozlabs.org> Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Michael Neuling authored
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Michael Neuling authored
Kconfig option for transactional memory on powerpc. Signed-off-by:
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Michael Neuling authored
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Michael Neuling authored
This adds the new transactional memory archtected state to the signal context in both 32 and 64 bit. Signed-off-by:
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Michael Neuling authored
This hooks the new transactional memory code into context switching, FP/VMX/VMX unavailable and exception return. Signed-off-by:
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Michael Neuling authored
We do lazy FP but not lazy TM (ie. userspace starts with MSR TM=1 FP=0). Hence if userspace does an FP instruction during a transaction, we'll take an fp unavailable exception. This adds functions needed to handle this case. We have to inject the current FP state into the checkpoint so that the hardware can decide what to do with the transaction. We can't inject only the FP so we have to do a full treclaim and recheckpoint to inject just the FP state. This will cause the transaction to be marked as aborted by the hardware. This just add the routines needed to do this for FP, VMX and VSX. It doesn't hook them into the rest of the code yet. Signed-off-by:
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Michael Neuling authored
These should never happen since we always turn on MSR TM when in userspace. We don't do lazy TM. Hence if we hit this, we barf and kill the task as something's gone horribly wrong. Signed-off-by:
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Michael Neuling authored
powerpc: Add reclaim and recheckpoint functions for context switching transactional memory processes When we switch out a task, we need to save both the checkpointed and the speculated state into the thread struct. Similarly when we are switching in a task we need to load both the checkpointed and speculated state. If the task was using FP, we non-lazily reload both the original and the speculative FP register states. This is because the kernel doesn't see if/when a TM rollback occurs, so if we take an FP unavoidable later, we are unable to determine which set of FP regs need to be restored. This simply adds these functions. It doesn't hook them into the existing code yet. Signed-off-by:
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Michael Neuling authored
This adds functions to restore the state of the FP/VSX registers from what's stored in the thread_struct. Two version for FP/VSX are required since one restores them from transactional/checkpoint side of the thread_struct and the other from the speculated side. Similar functions are added for VMX registers. Signed-off-by:
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Michael Neuling authored
Here we add the helper functions to be used when context switching. These allow us to fully reclaim and recheckpoint a transaction. We introduce a new paca field called tm_scratch to help us store away register values when doing the low level tm reclaim register save. Signed-off-by:
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Michael Neuling authored
Add transactional memory paca scratch register to show_regs. This is useful for debugging. Signed-off-by:
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Michael Neuling authored
Defines for MSR bits and transactional memory related SPRs TFIAR, TEXASR and TEXASRU. Signed-off-by:
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Michael Neuling authored
This adds new macros for saving and restoring checkpointed architected state from and to the thread_struct. It also adds some debugging macros for when your brain explodes trying to debug your transactional memory enabled kernel. Signed-off-by:
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Michael Neuling authored
Set of new archtected state for saving away on context switch. Signed-off-by:
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Michael Neuling authored
Here we define the new instructions we need for transactional memory in the kernel. This is so we can support compiling with binutils that don't support the new transactional memory instructions. Transactional memory results in two sets of architected state (GPRs/VSRs etc). treclaim allows us to read the checkpointed state (from the tbegin) so that we can store it away on a context switch. It does this by overwriting the exiting architected state, so you have to save that away before you treclaim. treclaim will also abort a transaction, so you can give a register value which contains an abort reason. trecheckpoint allows us to inject into the checkpointed state as if it were at the tbegin. It does this by copying the current architected state into the checkpointed state. Signed-off-by:
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Michael Neuling authored
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Michael Ellerman authored
In commit 466921c5 we added a hack to set the paca data_offset to zero so that per-cpu accesses would work on the boot cpu prior to per-cpu areas being setup. This fixed a problem with lockdep touching per-cpu areas very early in boot. However if we combine CONFIG_LOCK_STAT=y with any of the PPC_EARLY_DEBUG options, we can hit the same problem in udbg_early_init(). To avoid that we need to set the data_offset of the boot_paca also. So factor out the fixup logic and call it for both the boot_paca, and "the paca of the boot cpu". Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Tested-by:
Geoff Levand <geoff@infradead.org> Signed-off-by:
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Geoff Levand authored
The powerpc boot_paca symbol is now only used within the early_setup() routine, so move it from its global definition into early_setup(). Signed-off-by:
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Geoff Levand authored
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Geoff Levand authored
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Geoff Levand authored
To allow more control of the verbosity of ps3_result() add a check for the preprocessor macro PS3_VERBOSE_RESULT that builds a verbose verion of the ps3_result() routine. Signed-off-by:
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Paul Mackerras authored
Commit a413f474 ("powerpc: Disable relocation on exceptions whenever PR KVM is active") added calls to pSeries_disable_reloc_on_exc() and pSeries_enable_reloc_on_exc() to book3s_pr.c, and added declarations of those functions to <asm/hvcall.h>, but didn't add an include of <asm/hvcall.h> to book3s_pr.c. 64-bit kernels seem to get hvcall.h included via some other path, but 32-bit kernels fail to compile with: arch/powerpc/kvm/book3s_pr.c: In function ‘kvmppc_core_init_vm’: arch/powerpc/kvm/book3s_pr.c:1300:4: error: implicit declaration of function ‘pSeries_disable_reloc_on_exc’ [-Werror=implicit-function-declaration] arch/powerpc/kvm/book3s_pr.c: In function ‘kvmppc_core_destroy_vm’: arch/powerpc/kvm/book3s_pr.c:1316:4: error: implicit declaration of function ‘pSeries_enable_reloc_on_exc’ [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make[2]: *** [arch/powerpc/kvm/book3s_pr.o] Error 1 make[1]: *** [arch/powerpc/kvm] Error 2 make: *** [sub-make] Error 2 This fixes it by adding an include of hvcall.h. Signed-off-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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Paul Mackerras authored
The CFAR (Come-From Address Register) is a useful debugging aid that exists on POWER7 processors. Currently HV KVM doesn't save or restore the CFAR register for guest vcpus, making the CFAR of limited use in guests. This adds the necessary code to capture the CFAR value saved in the early exception entry code (it has to be saved before any branch is executed), save it in the vcpu.arch struct, and restore it on entry to the guest. Signed-off-by:
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Paul Mackerras authored
Some of the interrupt vectors on 64-bit POWER server processors are only 32 bytes long, which is not enough for the full first-level interrupt handler. For these we currently just have a branch to an out-of-line handler. However, this means that we corrupt the CFAR (come-from address register) on POWER7 and later processors. To fix this, we split the EXCEPTION_PROLOG_1 macro into two pieces: EXCEPTION_PROLOG_0 contains the part up to the point where the CFAR is saved in the PACA, and EXCEPTION_PROLOG_1 contains the rest. We then put EXCEPTION_PROLOG_0 in the short interrupt vectors before we branch to the out-of-line handler, which contains the rest of the first-level interrupt handler. To facilitate this, we define new _OOL (out of line) variants of STD_EXCEPTION_PSERIES, etc. In order to get EXCEPTION_PROLOG_0 to be short enough, i.e., no more than 6 instructions, it was necessary to move the stores that move the PPR and CFAR values into the PACA into __EXCEPTION_PROLOG_1 and to get rid of one of the two HMT_MEDIUM instructions. Previously there was a HMT_MEDIUM_PPR_DISCARD before the prolog, which was nop'd out on processors with the PPR (POWER7 and later), and then another HMT_MEDIUM inside the HMT_MEDIUM_PPR_SAVE macro call inside __EXCEPTION_PROLOG_1, which was nop'd out on processors without PPR. Now the HMT_MEDIUM inside EXCEPTION_PROLOG_0 is there unconditionally and the HMT_MEDIUM_PPR_DISCARD is not strictly necessary, although this leaves it in for the interrupt vectors where there is room for it. Previously we had a handler for hypervisor maintenance interrupts at 0xe50, which doesn't leave enough room for the vector for hypervisor emulation assist interrupts at 0xe40, since we need 8 instructions. The 0xe50 vector was only used on POWER6, as the HMI vector was moved to 0xe60 on POWER7. Since we don't support running in hypervisor mode on POWER6, we just remove the handler at 0xe50. This also changes denorm_exception_hv to use EXCEPTION_PROLOG_0 instead of open-coding it, and removes the HMT_MEDIUM_PPR_DISCARD from the relocation-on vectors (since any CPU that supports relocation-on interrupts also has the PPR). Signed-off-by:
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Paul Mackerras authored
The Cell processor doesn't support relocation-on interrupts, so we don't need relocation-on versions of the interrupt vectors that are purely Cell-specific. This removes them. Signed-off-by:
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- 13 Feb, 2013 4 commits
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Po Liu authored
This facilitates getting the physical address of the SEC node. Signed-off-by:
Liu po <po.liu@freescale.com> Reviewed-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Holger Brunck authored
Synchronize this defconfig with latest kernel version. Signed-off-by:
Holger Brunck <holger.brunck@keymile.com> Signed-off-by:
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Gerlando Falauto authored
There is no point in applying this quirk when par_io is not present. Signed-off-by:
Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by:
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Gerlando Falauto authored
Move the code for this quirk to a dedicated function. Signed-off-by:
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