- 05 Sep, 2019 2 commits
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Ryder Lee authored
Add a pre-computed text length to avoid uninitialized value in the check. Fixes: e4727066 ("crypto: mediatek - Add empty messages check in GCM mode") Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Signed-off-by:
Vic Wu <vic.wu@mediatek.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Ryder Lee authored
Move mtk_aes_find_dev() to right functions as nobody uses the 'cryp' under current flows. We can also avoid duplicate checks here and there in this way. Signed-off-by:
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- 30 Aug, 2019 33 commits
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Mao Wenan authored
When CRYPTO_DEV_HISI_SEC=y, below compilation error is found after 'commit 894b68d8 ("crypto: hisilicon/des - switch to new verification routines")': drivers/crypto/hisilicon/sec/sec_algs.o: In function `sec_alg_skcipher_setkey_des_cbc': sec_algs.c:(.text+0x11f0): undefined reference to `des_expand_key' drivers/crypto/hisilicon/sec/sec_algs.o: In function `sec_alg_skcipher_setkey_des_ecb': sec_algs.c:(.text+0x1390): undefined reference to `des_expand_key' make: *** [vmlinux] Error 1 This because DES library has been moved to lib/crypto in this commit '04007b0e ("crypto: des - split off DES library from generic DES cipher driver")'. Fix this by selecting CRYPTO_LIB_DES in CRYPTO_DEV_HISI_SEC. Fixes: 04007b0e ("crypto: des - split off DES library from generic DES cipher driver") Fixes: 894b68d8 ("crypto: hisilicon/des - switch to new verification routines") Signed-off-by:
Mao Wenan <maowenan@huawei.com> Acked-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by:
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Hans de Goede authored
lib/crypto/sha256.c / lib/crypto/libsha256.o may end up being a module, so it needs a MODULE_LICENSE() line, add this. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Ard Biesheuvel authored
For correctness and compliance with the XTS-AES specification, we are adding support for ciphertext stealing to XTS implementations, even though no use cases are known that will be enabled by this. Since the ccp driver already has a fallback skcipher standby for dealing with input sizes other than [16, 512, 1024, 2048, 4096], just drop the check against the block size. Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gary Hook <gary.hook@amd.com> Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by:
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YueHaibing authored
drivers/crypto/nx/nx.h:12:19: warning: nx_driver_string defined but not used [-Wunused-const-variable=] drivers/crypto/nx/nx.h:13:19: warning: nx_driver_version defined but not used [-Wunused-const-variable=] They are never used, so just remove it. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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YueHaibing authored
drivers/crypto/atmel-i2c.h:68:3: warning: error_list defined but not used [-Wunused-const-variable=] error_list is only used in atmel-i2c.c, so just move the definition over there. Reported-by:
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YueHaibing authored
crypto/aegis.h:27:32: warning: crypto_aegis_const defined but not used [-Wunused-const-variable=] crypto_aegis_const is only used in aegis128-core.c, just move the definition over there. Reported-by:
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Andrey Smirnov authored
Add clock entry needed to support i.MX8MQ. Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Spencer <christopher.spencer@sea.co.uk> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Horia Geantă <horia.geanta@nxp.com> Cc: Aymen Sghaier <aymen.sghaier@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Andrey Smirnov authored
Per feedback from NXP tech support the way to use register based service interface on i.MX8MQ is to follow the same set of steps outlined for the case when virtualization is enabled, regardless if it is. Current version of SRM for i.MX8MQ speaks of DECO DID_MS and DECO DID_LS registers, but apparently those are not implemented, so the case when SCFGR[VIRT_EN]=0 should be handled the same as the case when SCFGR[VIRT_EN]=1 Signed-off-by:
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Andrey Smirnov authored
i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation, so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer size. Convert the code to query CTPR and MCFGR for that during driver probing. Signed-off-by:
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Andrey Smirnov authored
Using dma_addr_t for elements of JobR input ring is not appropriate on all 64-bit SoCs, some of which, like i.MX8MQ, use only 32-bit wide pointers there. Convert all of the code to use explicit helper function that can be later extended to support i.MX8MQ. No functional change intended. Signed-off-by:
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Andrey Smirnov authored
Using struct jr_outentry to specify the layout of JobR output ring is not appropriate for all 64-bit SoC, since some of them, like i.MX8MQ, use 32-bit pointers there which doesn't match 64-bit dma_addr_t. Convert existing code to use explicit helper functions to access any of the JobR output ring elements, so that the support for i.MX8MQ can be added later. No functional change intended. Signed-off-by:
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Andrey Smirnov authored
Instead of selecting the implementation of cpu_to_caam_dma()/caam_dma_to_cpu() at build time using the preprocessor, convert the code to do that at run-time using IS_ENABLED macro. This is needed to add support for i.MX8MQ. No functional change intended. Signed-off-by:
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Andrey Smirnov authored
In order to be able to configure CAAM pointer size at run-time, which needed to support i.MX8MQ, which is 64-bit SoC with 32-bit pointer size, convert CAAM_PTR_SZ to refer to a global variable of the same name ("caam_ptr_sz") and adjust the rest of the code accordingly. No functional change intended. Signed-off-by: -
Andrey Smirnov authored
Both qi.h and cammalg_qi2.h seem to define identical versions of MAX_SDLEN. Move it to desc_constr.h to avoid duplication. Signed-off-by:
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Andrey Smirnov authored
Since 32-bit of both wr_reg64 and rd_reg64 now use 64-bit IO helpers, these functions should no longer be necessary. No functional change intended. Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Cc: Chris Spencer <christopher.spencer@sea.co.uk> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Horia Geantă <horia.geanta@nxp.com> Cc: Aymen Sghaier <aymen.sghaier@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Andrey Smirnov authored
Following the same transformation logic as outlined in previous commit converting wr_reg64, convert rd_reg64 to use helpers from <linux/io-64-nonatomic-hi-lo.h> first. No functional change intended. Signed-off-by:
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Andrey Smirnov authored
In order to be able to unify 64 and 32 bit implementations of wr_reg64, let's convert it to use helpers from <linux/io-64-nonatomic-hi-lo.h> first. Here are the steps of the transformation: 1. Inline wr_reg32 helpers: if (!caam_imx && caam_little_end) { if (caam_little_end) { iowrite32(data >> 32, (u32 __iomem *)(reg) + 1); iowrite32(data, (u32 __iomem *)(reg)); } else { iowrite32be(data >> 32, (u32 __iomem *)(reg) + 1); iowrite32be(data, (u32 __iomem *)(reg)); } } else { if (caam_little_end) { iowrite32(data >> 32, (u32 __iomem *)(reg)); iowrite32(data, (u32 __iomem *)(reg) + 1); } else { iowrite32be(data >> 32, (u32 __iomem *)(reg)); iowrite32be(data, (u32 __iomem *)(reg) + 1); } } 2. Transfrom the conditionals such that the check for 'caam_little_end' is at the top level: if (caam_little_end) { if (!caam_imx) { iowrite32(data >> 32, (u32 __iomem *)(reg) + 1); iowrite32(data, (u32 __iomem *)(reg)); } else { iowrite32(data >> 32, (u32 __iomem *)(reg)); iowrite32(data, (u32 __iomem *)(reg) + 1); } } else { iowrite32be(data >> 32, (u32 __iomem *)(reg)); iowrite32be(data, (u32 __iomem *)(reg) + 1); } 3. Invert the check for !caam_imx: if (caam_little_end) { if (caam_imx) { iowrite32(data >> 32, (u32 __iomem *)(reg)); iowrite32(data, (u32 __iomem *)(reg) + 1); } else { iowrite32(data >> 32, (u32 __iomem *)(reg) + 1); iowrite32(data, (u32 __iomem *)(reg)); } } else { iowrite32be(data >> 32, (u32 __iomem *)(reg)); iowrite32be(data, (u32 __iomem *)(reg) + 1); } 4. Make use of iowrite64* helpers from <linux/io-64-nonatomic-hi-lo.h> if (caam_little_end) { if (caam_imx) { iowrite32(data >> 32, (u32 __iomem *)(reg)); iowrite32(data, (u32 __iomem *)(reg) + 1); } else { iowrite64(data, reg); } } else { iowrite64be(data, reg); } No functional change intended. Signed-off-by: -
Andrey Smirnov authored
In order to avoid any risk of JR IRQ request being handled while some of the resources used for that are not yet allocated move the code requesting said IRQ to the endo of caam_jr_init(). Signed-off-by:
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Andrey Smirnov authored
Use devres to allocate all of the resources in caam_jr_init() (DMA coherent and regular memory, IRQs) drop calls to corresponding deallocation routines. No functional change intended. Signed-off-by:
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Andrey Smirnov authored
Simplify clock initialization code by converting it to use clk-bulk, devres and soc_device_match() match table. No functional change intended. Signed-off-by:
Leonard Crestez <leonard.crestez@nxp.com> Tested-by:
Iuliana Prodan <iuliana.prodan@nxp.com> Cc: Chris Spencer <christopher.spencer@sea.co.uk> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Horia Geantă <horia.geanta@nxp.com> Cc: Aymen Sghaier <aymen.sghaier@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Andrey Smirnov authored
Exactly the same code to figure out DMA mask is repeated twice in the driver code. To avoid repetition, move that logic into a standalone subroutine in intern.h. While at it re-shuffle the code to make it more readable with early returns. Signed-off-by:
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Iuliana Prodan authored
Use print_hex_dump_debug function to print debug messages, instead of print_hex_dump inside #ifdef DEBUG. Fixes: 6e005503 ("crypto: caam - print debug messages at debug level") Signed-off-by:
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Pascal van Leeuwen authored
Until now, the inside-secure driver required a set of firmware images supplied by the silicon vendor, typically under NDA, to be present in /lib/firmware/inside-secure in order to be able to function. This patch removes the dependence on this official vendor firmware by falling back to generic "mini" FW - developed specifically for this driver - that can be provided under GPL 2.0 through linux-firmwares. Signed-off-by:
Pascal van Leeuwen <pvanleeuwen@verimatrix.com> Acked-by:
Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by:
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Pascal van Leeuwen authored
This patch adds support for a PCIE development board with FPGA from Xilinx, to facilitate pre-silicon driver development by both Inside Secure and its IP customers. Since Inside Secure neither produces nor has access to actual silicon, this is required functionality to allow us to contribute. Signed-off-by:
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Pascal van Leeuwen authored
This removes some code determine which engine has which algorithms which was effectively redundant (may have been forward-looking?) due to always enabling all algorithms for all currently supported engines. A future patch will use a different, more scalable approach to achieve this. This is removed now because otherwise the next patch will add new hardware which would otherwise have to be added to all algorithms, so now is a convenient time to just get rid of this. Signed-off-by:
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Pascal van Leeuwen authored
While being a generic EIP97/EIP197 driver, the driver was only selectable for Marvell Armada hardware. This fix makes the driver selectable for any Device Tree supporting kernel configuration, allowing it to be used for other compatible hardware by just adding the correct device tree entry. It also allows the driver to be selected for PCI(E) supporting kernel con- figurations, to be able to use it with PCIE based FPGA development boards for pre-silicon driver development by both Inside Secure and its IP custo- mers. Signed-off-by:
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Ard Biesheuvel authored
Align the s5p ctr(aes) implementation with other implementations of the same mode, by setting the block size to 1. Signed-off-by:
Kamil Konieczny <k.konieczny@partner.samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Ard Biesheuvel authored
The s5p skcipher driver returns -EINVAL for zero length inputs, which deviates from the behavior of the generic ECB template, and causes fuzz tests to fail. In cases where the input is not a multiple of the AES block size (and the chaining mode is not CTR), it prints an error to the kernel log, which is a thing we usually try to avoid in response to situations that can be triggered by unprivileged users. Signed-off-by:
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Ard Biesheuvel authored
Add an accelerated version of the 'essiv(cbc(aes),sha256)' skcipher, which is used by fscrypt or dm-crypt on systems where CBC mode is signficantly more performant than XTS mode (e.g., when using a h/w accelerator which supports the former but not the latter) This avoids a separate call into the AES cipher for every invocation. Signed-off-by:
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Ard Biesheuvel authored
The plain CBC driver and the CTS one share some code that iterates over a scatterwalk and invokes the CBC asm code to do the processing. The upcoming ESSIV/CBC mode will clone that pattern for the third time, so let's factor it out first. Signed-off-by:
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Ard Biesheuvel authored
Add a test vector for the ESSIV mode that is the most widely used, i.e., using cbc(aes) and sha256, in both skcipher and AEAD modes (the latter is used by tcrypt to encapsulate the authenc template or h/w instantiations of the same) Signed-off-by:
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Ard Biesheuvel authored
When building the new aegis128 NEON code in big endian mode, Clang complains about the const uint8x16_t permute vectors in the following way: crypto/aegis128-neon-inner.c:58:40: warning: vector initializers are not compatible with NEON intrinsics in big endian mode [-Wnonportable-vector-initialization] static const uint8x16_t shift_rows = { ^ crypto/aegis128-neon-inner.c:58:40: note: consider using vld1q_u8() to initialize a vector from memory, or vcombine_u8(vcreate_u8(), vcreate_u8()) to initialize from integer constants Since the same issue applies to the uint8x16x4_t loads of the AES Sbox, update those references as well. However, since GCC does not implement the vld1q_u8_x4() intrinsic, switch from IS_ENABLED() to a preprocessor conditional to conditionally include this code. Reported-by:Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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Christophe JAILLET authored
The help section says that the module will be called 'pipcoxcell_crypto'. This is likely a typo. Use 'picoxcell_crypto' instead Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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- 22 Aug, 2019 5 commits
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Herbert Xu authored
This patch removes the variable flags which is now unused thanks to the new DES helpers. Fixes: 9d574ae8 ("crypto: talitos/des - switch to new...") Signed-off-by:
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Ard Biesheuvel authored
Fix build breakage caused by the DES library refactor. Fixes: d4b90dbc ("crypto: n2/des - switch to new verification routines") Signed-off-by:
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Ard Biesheuvel authored
Fix a typo XTS_BLOCKSIZE -> XTS_BLOCK_SIZE, causing the build to break. Fixes: ce68acbc ("crypto: s390/xts-aes - invoke fallback for...") Signed-off-by:
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Hans de Goede authored
Drop the duplicate generic sha256 (and sha224) implementation from crypto/sha256_generic.c and use the implementation from lib/crypto/sha256.c instead. "diff -u lib/crypto/sha256.c sha256_generic.c" shows that the core sha256_transform function from both implementations is identical and the other code is functionally identical too. Suggested-by:
Eric Biggers <ebiggers@kernel.org> Signed-off-by:
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Hans de Goede authored
Add sha224 support to the lib/crypto/sha256 library code. This will allow us to replace both the sha256 and sha224 parts of crypto/sha256_generic.c when we remove the code duplication in further patches in this series. Suggested-by:
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