- 05 Oct, 2021 5 commits
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Guchun Chen authored
In current code, when a PCI error state pci_channel_io_normal is detectd, it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI driver will continue the execution of PCI resume callback report_resume by pci_walk_bridge, and the callback will go into amdgpu_pci_resume finally, where write lock is releasd unconditionally without acquiring such lock first. In this case, a deadlock will happen when other threads start to acquire the read lock. To fix this, add a member in amdgpu_device strucutre to cache pci_channel_state, and only continue the execution in amdgpu_pci_resume when it's pci_channel_io_frozen. Fixes: c9a6b82f ("drm/amdgpu: Implement DPC recovery") Suggested-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Make sure that we notice this in error reports. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Christian König authored
This reverts commit 728e7e0c. Further discussion reveals that this feature is severely broken and needs to be reverted ASAP. GPU reset can never be delayed by userspace even for debugging or otherwise we can run into in kernel deadlocks. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch is to fix clinfo failure in Raven/Picasso: Number of platforms: 1 Platform Profile: FULL_PROFILE Platform Version: OpenCL 2.2 AMD-APP (3364.0) Platform Name: AMD Accelerated Parallel Processing Platform Vendor: Advanced Micro Devices, Inc. Platform Extensions: cl_khr_icd cl_amd_event_callback Platform Name: AMD Accelerated Parallel Processing Number of devices: 0 Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Tested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Yifan Zhang authored
kfd_resume doesn't involve iommu operation, remove redundant iommu cleanup code. Signed-off-by:
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- 04 Oct, 2021 35 commits
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Alex Deucher authored
Depends on DRM_AMDGPU_SI and DRM_AMD_DC Reviewed-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Wyatt Wood authored
[Why] Running into bugchecks during stress test where rptr is 0xFFFFFFFF. Typically this is caused by a hard hang, and can come from HW outside of DCN. [How] To prevent bugchecks when writing the DMUB rptr, fist check that the rptr is valid. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alex Deucher authored
No need for a separate kconfig option at this point. Reviewed-by:
Zhan Liu <zhan.liu@amd.com> Signed-off-by:
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Guo Zhengkui authored
Remove two repeated includings in line 46 and 47. Acked-by:
Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by:
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Lijo Lazar authored
In the rare event when GFX IP suspend coincides with a s0ix entry, don't schedule a delayed work, instead signal PMFW immediately to allow GFXOFF entry. GFXOFF is a prerequisite for s0ix entry. PMFW needs to be signaled about GFXOFF status before amd-pmc module passes OS HINT to PMFW telling that everything is ready for a safe s0ix entry. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1712Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciell@amd.com> Signed-off-by:
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Alex Deucher authored
Not sure why that was there. Remove it. Reviewed-by:
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Alex Deucher authored
IP_VERSION(11, 0, 13) does the exact same thing as IP_VERSION(11, 0, 12) so squash them together. Reviewed-by:
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James Zhu authored
Add jpeg2.6 start/end with updated PCTL0_MMHUB_DEEPSLEEP_IB address. Signed-off-by:
Leo Liu <leo.lilu@amd.com> Signed-off-by:
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James Zhu authored
Move jpeg2 shared macro to header file Signed-off-by:
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Lang Yu authored
Memory is allocated for ttm->sg by kmalloc in kfd_mem_dmamap_userptr, but isn't freed by kfree in kfd_mem_dmaunmap_userptr. Free it! Fixes: 264fb4d3 ("drm/amdgpu: Add multi-GPU DMA mapping helpers") Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
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Alex Deucher authored
If you set amdgpu.discovery=2 you can force the the driver to fetch the IP discovery table from a file rather than from the table shipped on the device. This is useful for debugging and for device bring up and emulation when the tables may be in flux. Reviewed-by:
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Alex Deucher authored
rather than asic type. v2: fix up CZ case Acked-by:
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Alex Deucher authored
We can get the pdev and asic type from the adev. No need to pass them explicitly. v2: squash in build fix for !CONFIG_HSA_AMD from Anson Reviewed-by:
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Alex Deucher authored
Handle SRIOV requirements when adding IP blocks. v2: add comment about UVD/VCE support on vega20 SR-IOV Acked-by:
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Alex Deucher authored
Split into several smaller per IP functions to make it easier to handle ordering issues for things like SR-IOV in a follow up patch. Acked-by:
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Alex Deucher authored
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by:
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Alex Deucher authored
For new chips with no explicit entry in the PCI ID list. Reviewed-by:
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Alex Deucher authored
Add a new asic type for asics where we don't have an explicit entry in the PCI ID list. We don't need an asic type for these asics, other than something higher than the existing ones, so just use this for all new asics. Reviewed-by:
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Alex Deucher authored
Default to PSP ucode loading unless the user specifies direct. Acked-by:
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Alex Deucher authored
Use the table rather than asic specific harvest registers. v2: remove harvesting register checking Signed-off-by: -
Alex Deucher authored
Handled by IP discovery now. Acked-by:
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Alex Deucher authored
Handled by IP discovery now. Acked-by:
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Alex Deucher authored
Rather than hardcoding it. We already have the number of VCN instances from a previous patch, so just update the VCN instances for chips with static tables. v2: squash in checks for SDMA3,4 (Guchun) v3: clarify VCN changes Reviewed-by:
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Guchun Chen authored
They are missed. Acked-by:
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Alex Deucher authored
So we can store the VCN IP revision for each instance of VCN. Acked-by:
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Guchun Chen authored
Otherwise, we will run into error case path. v2: fix build when CONFIG_DRM_AMD_DC_DCN is not set Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: squash in fix for navy flounder and sienna cichlid Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: switch if statement to a switch statement Acked-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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