- 01 Sep, 2021 9 commits
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Jude Shih authored
[WHY] To add support for HPD interrupt handling from DMUB. HPD interrupt could be triggered from outbox1 from DMUB [HOW] 1) Use queue_work to handle hpd task from outbox1 2) Add handle_hpd_irq_helper to share interrupt handling code between legacy and DMUB HPD from outbox1 3) Added DMUB HPD handling in dmub_srv_stat_get_notification(). HPD handling callback function and wake up the DMUB thread. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Jude Shih <shenshih@amd.com> Tested-by:
Daniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Josip Pavic authored
[Why] Some ABM registers don't exist on DCN 3.01, so are missing from its register offset list. However, this list was copied to later versions of DCN that do have these registers. As a result, they're inaccessible from the driver on those DCN versions even though they exist. [How] Add the missing ABM register offsets to DCN 3.02+ Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Fangzhi Zuo authored
1. Retrieve 128/132b link cap. 2. 128/132b link training and payload allocation. 3. UHBR10 link rate support. [squash in warning fixes - Alex] Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Fangzhi Zuo authored
Parse DP2 encoder caps and hpo instance from bios Signed-off-by:
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Fangzhi Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | | +--------------------+ | | v ===============|============= v +------------------+ | DIO Output Mux | +------------------+ | v +-----+ | PHY | +-----+ | PHYD32CLK[0] v +------+ | DCCG | +------+ | v SYMCLK32 Signed-off-by: -
Fangzhi Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | v +--------------------+ [squash in warning fixes - Alex] Signed-off-by: -
Fangzhi Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | v v v v +----------------------+ | HPO Stream Encoder | +----------------------+ [squash in warning fixes - Alex] Signed-off-by: -
Fangzhi Zuo authored
HW Blocks: +-----+ | HDA | +-----+ | | HPO ===============|============= | v | +-----+ | | APG | v +-----+ Signed-off-by: -
Alex Sierra authored
During svm restore pages interrupt handler, kfd_process ref count was never dropped when xnack was disabled. Therefore, the object was never released. Fixes: 2383f56b ("drm/amdkfd: page table restore through svm API") Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Philip Yang <philip.yang@amd.com> Reviewed-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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- 31 Aug, 2021 8 commits
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Jiawei Gu authored
Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under SRIOV 1-VF scenario. Signed-off-by:
Jiawei Gu <Jiawei.Gu@amd.com> Signed-off-by:
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Philip Yang authored
Get process vm root BO ref in case process is exiting and root BO is freed, to avoid NULL pointer dereference backtrace: BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 Call Trace: amdgpu_show_fdinfo+0xfe/0x2a0 [amdgpu] seq_show+0x12c/0x180 seq_read+0x153/0x410 vfs_read+0x91/0x140[ 3427.206183] ksys_read+0x4f/0xb0 do_syscall_64+0x5b/0x1a0 entry_SYSCALL_64_after_hwframe+0x65/0xca Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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xinhui pan authored
Fall through to handle the error instead of return. Fixes: f8aab604 ("drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs") Cc: stable@vger.kernel.org Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Guchun Chen authored
This gurantees no more work on the ring can be submitted to hardware in suspend/resume case, otherwise a potential race will occur and the ring will get no chance to stay empty before suspend. v2: Call drm_sched_resubmit_job before drm_sched_start to restart jobs from the pending list. Suggested-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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John Clements authored
Resolve incorrect register address Reviewed-by:
Candice Li <candice.li@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] lt_settings' pointers remain uninitialized but nonzero if display fails to light up with no DPCD/EDID info populated, leading to a hang on access Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Angus Wang authored
[WHY] The change has caused high idle memory clock speed and power consumption at some resolutions and frame rates for Navi10 [HOW] Reverted change "drm/amd/display: Fixed Intermittent blue screen on OLED panel" Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Angus Wang <angus.wang@amd.com> Tested-by:
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Anson Jacob authored
Free memory allocated if any of the previous allocations failed. >>> CID 1487129: Resource leaks (RESOURCE_LEAK) >>> Variable "vpg" going out of scope leaks the storage it points to. Addresses-Coverity-ID: 1487129: ("Resource leaks") Reviewed-by:Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
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- 30 Aug, 2021 13 commits
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Colin Ian King authored
There are three identical spelling mistakes in dev_err messages. Fix these. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Koba Ko authored
Due to high latency in PCIE clock switching on RKL platforms, switching the PCIE clock dynamically at runtime can lead to HDMI/DP audio problems. On newer asics this is handled in the SMU firmware. For SMU7-based asics, disable PCIE clock switching to avoid the issue. AMD provide a parameter to disable PICE_DPM. modprobe amdgpu ppfeaturemask=0xfff7bffb It's better to contorl PCIE_DPM in amd gpu driver, switch PCI_DPM by determining intel RKL platform for SMU7-based asics. Fixes: 1a31474c ("drm/amd/pm: workaround for audio noise issue") Ref: https://lists.freedesktop.org/archives/amd-gfx/2021-August/067413.htmlSigned-off-by:
Koba Ko <koba.ko@canonical.com> Signed-off-by:
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Lang Yu authored
To cover the corner case that people want to know the ID of an UNKNOWN CMD. Suggested-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Aaron Liu authored
Scatter/gather is APU feature starting from carrizo. adev->apu_flags is not used for all APUs. adev->flags & AMD_IS_APU can be used for all APUs. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
Missing code for Yellow Carp to enable scatter gather - follows how DCN21 support was added. Tested that 8k framebuffer allocation and display can now succeed after applying the patch. v2: Add hookup in DM Reviewed-by:
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Kees Cook authored
In preparation for FORTIFY_SOURCE performing compile-time and run-time field bounds checking for memcpy(), memmove(), and memset(), avoid intentionally writing across neighboring fields. The "Board Parameters" members of the structs: struct atom_smc_dpm_info_v4_5 struct atom_smc_dpm_info_v4_6 struct atom_smc_dpm_info_v4_7 struct atom_smc_dpm_info_v4_10 are written to the corresponding members of the corresponding PPTable_t variables, but they lack destination size bounds checking, which means the compiler cannot verify at compile time that this is an intended and safe memcpy(). Since the header files are effectively immutable[1] and a struct_group() cannot be used, nor a common struct referenced by both sides of the memcpy() arguments, add a new helper, amdgpu_memcpy_trailing(), to perform the bounds checking at compile time. Replace the open-coded memcpy()s with amdgpu_memcpy_trailing() which includes enough context for the bounds checking. "objdump -d" shows no object code changes. [1] https://lore.kernel.org/lkml/e56aad3c-a06f-da07-f491-a894a570d78f@amd.com Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Feifei Xu <Feifei.Xu@amd.com> Cc: Likun Gao <Likun.Gao@amd.com> Cc: Jiawei Gu <Jiawei.Gu@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Evan Quan authored
This reverts the commit below: "drm/amdgpu: disable BACO support for 699F:C7 polaris12 SKU temporarily". As the S3 hang issue has been fixed by another commit: "drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend". Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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YuBiao Wang authored
Send response to host after received the flr notification from host. Port NV change to vega10. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
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Alex Deucher authored
New PCI IDs. Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yifan Zhang authored
The parameters were renamed. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Luben Tuikov authored
We can now process any RAS EEPROM address from VBIOS. Generalize so as to compute the top three bits of the 19-bit EEPROM address, from any byte returned as the "i2c address" from VBIOS. Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Luben Tuikov authored
1) Generalize the function--if the user didn't set i2c_address, still return true/false to indicate whether VBIOS contains the RAS EEPROM address. This function shouldn't evaluate whether the user set the i2c_address pointer or not. 2) Don't touch the caller's i2c_address, unless you have to--this function shouldn't have side effects. 3) Correctly set the function comment as a kernel-doc comment. Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by:
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Jing Yangyang authored
./drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c:112:9-10:WARNING: return of 0/1 in function 'dcn31_is_panel_backlight_on' with return type bool ./drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c:122:9-10:WARNING: return of 0/1 in function 'dcn31_is_panel_powered_on' with return type bool Return statements in functions returning bool should use true/false instead of 1/0. Generated by: scripts/coccinelle/misc/boolreturn.cocci Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Jing Yangyang <jing.yangyang@zte.com.cn> Signed-off-by:
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- 29 Aug, 2021 2 commits
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Dave Airlie authored
Merge tag 'amd-drm-next-5.15-2021-08-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.15-2021-08-27: amdgpu: - PLL fix for SI - Misc code cleanups - RAS fixes - PSP cleanups - Polaris UVD/VCE suspend fixes - aldebaran fixes - DCN3.x mclk fixes amdkfd: - CWSR fixes for arcturus and aldebaran - SVM fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210827192336.4649-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2021-08-26' of git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 fixes for v5.15-rc1: - Disable underrun recovery with eDP MSO panels on ADL-P - Use designated initializers for init/exit table - Fix some error pointer usages Signed-off-by:
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- 26 Aug, 2021 8 commits
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Nicholas Kazlauskas authored
[Why] This is a global parameter, not a per pipe parameter and it's useful for experimenting with the prefetch schedule to be adjustable from the SOC bb. [How] Add a parameter to the SOC bb, default is the existing policy for all DCN. Fill it in when filling SOC bb parameters. Revert the policy to use MinDCFClk at the same time since that's not going to give us P-State in most cases on the spreadsheet. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why & How] DML is initialized again unnecessarily after its done conditionally. Remove the duplicate initialization Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403Signed-off-by:
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Jerry (Fangzhi) Zuo authored
[Why] Drop hardcoded dispclk, dppclk, phyclk [How] Read the corresponding values from clock table entries already populated. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 Cc: stable@vger.kernel.org Signed-off-by:
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Aurabindo Pillai authored
[Why & How] The DCN3 SoC parameter num_states was calculated but not saved into the object. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 Cc: stable@vger.kernel.org Signed-off-by:
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Hawking Zhang authored
disable GFX CGCG and CGLS to workaround a hardware issue found in aldebaran. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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John Clements authored
resolve register address issue for detecting/clearing RAS interrupt Reviewed-by:
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John Clements authored
Update XGMI RAS to support error query on aldebaran Reviewed-by:
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Sean Keely authored
On systems with multiple SH per SE compute_static_thread_mgmt_se# is split into independent masks, one for each SH, in the upper and lower 16 bits. We need to detect this and apply cu masking to each SH. The cu mask bits are assigned first to each SE, then to alternate SHs, then finally to higher CU id. This ensures that the maximum number of SPIs are engaged as early as possible while balancing CU assignment to each SH. v2: Use max SH/SE rather than max SH in cu_per_sh. v3: Fix comment blocks, ensure se_mask is initially zero filled, and correctly assign se.sh.cu positions to unset bits in cu_mask. Signed-off-by:Sean Keely <Sean.Keely@amd.com> Reviewed-by:
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