- 07 Dec, 2006 40 commits
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Duncan Sands authored
Since v->counter is both read and written, it should be an output as well as an input for the asm. The current code only gets away with this because counter is volatile. Also, according to Documents/atomic_ops.txt, atomic_add_return should provide a memory barrier, in particular a compiler barrier, so the asm should be marked as clobbering memory. Test case: #include <stdio.h> typedef struct { int counter; } atomic_t; /* NB: no "volatile" */ #define ATOMIC_INIT(i) { (i) } #define atomic_read(v) ((v)->counter) static __inline__ int atomic_add_return(int i, atomic_t *v) { int __i = i; __asm__ __volatile__( "lock; xaddl %0, %1;" :"=r"(i) :"m"(v->counter), "0"(i)); /* __asm__ __volatile__( "lock; xaddl %0, %1" :"+r" (i), "+m" (v->counter) : : "memory"); */ return i + __i; } int main (void) { atomic_t a = ATOMIC_INIT(0); int x; x = atomic_add_return (1, &a); if ((x!=1) || (atomic_read(&a)!=1)) printf("fail: %i, %i\n", x, atomic_read(&a)); } Signed-off-by:Duncan Sands <baldrick@free.fr> Signed-off-by:
Andi Kleen <ak@suse.de> Cc: Andi Kleen <ak@suse.de> Acked-by:
David Howells <dhowells@redhat.com> Signed-off-by:
Andrew Morton <akpm@osdl.org>
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Vivek Goyal authored
Correct the documentation for bzImage protocol extension due to relocatable bzImage. Signed-off-by:
Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by:
"H. Peter Anvin" <hpa@zytor.com> Signed-off-by:
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Burman Yan authored
Cc: Andi Kleen <ak@suse.de> Signed-off-by:
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Randy Dunlap authored
CC arch/i386/boot/compressed/misc.o arch/i386/boot/compressed/misc.c:120: error: static declaration of 'xquad_portio' follows non-static declaration include/asm/io.h:275: error: previous declaration of 'xquad_portio' was here make[2]: *** [arch/i386/boot/compressed/misc.o] Error 1 Signed-off-by:
Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by:
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Adrian Bunk authored
Nothing in include/asm-x86_64/cpufeature.h is part of the userspace<->kernel interface. Signed-off-by:
Adrian Bunk <bunk@stusta.de> Signed-off-by:
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Jan Beulich authored
Add debugging printks to the unwinder to allow easier debugging when something goes wrong with it. This can be controlled with the new unwinder_debug=N option Most output is given by N=1 AK: Added documentation of unwinder_debug= Signed-off-by:
Jan Beulich <jbeulich@novell.com> Signed-off-by:
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Andi Kleen authored
- Remove "Disabling IOMMU" message because it confuses people - Clarify that the GART IOMMU is refered to in other message Signed-off-by: -
Venkatesh Pallipadi authored
Idle callbacks has some races when enter_idle() sets isidle and subsequent interrupts that can happen on that CPU, before CPU goes to idle. Due to this, an IDLE_END can get called before IDLE_START. To avoid these races, disable interrupts before enter_idle and make sure that all idle routines do not enable interrupts before entering idle. Note that poll_idle() still has a this race as it has to enable interrupts before going to idle. But, all other idle routines have the race fixed. Signed-off-by:
Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by:
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Andi Kleen authored
This was added as a workaround for the fallback unwinder not supporting unaligned stack pointers properly. But now it was fixed to do that, so it's not needed anymore Cc: mingo@elte.hu Signed-off-by: -
Jan Beulich authored
Tighten the requirements on both input to and output from the Dwarf2 unwinder. Signed-off-by:
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Andi Kleen authored
Shouldn't be needed anymore since __kernel_text_address is used unconditionally on x86-64 Signed-off-by: -
Andi Kleen authored
We're already well protected against module unloads because module unload uses stop_machine(). The only exception is NMIs, but other users already risk lockless accesses here. This avoids some hackery in lockdep and also a potential deadlock This matches what i386 does. Signed-off-by: -
Andi Kleen authored
This avoids trouble with the page fault handler if the fault happens inside an interrupt context. Suggested by Linus Cc: jbeulich@novell.com Signed-off-by: -
Arjan van de Ven authored
On the Core2 cpus, the rdtsc instruction is not serializing (as defined in the architecture reference since rdtsc exists) and due to the deep speculation of these cores, it's possible that you can observe time go backwards between cores due to this speculation. Since the kernel already deals with this with the SYNC_RDTSC flag, the solution is simple, only assume that the instruction is serializing on family 15... The price one pays for this is a slightly slower gettimeofday (by a dozen or two cycles), but that increase is quite small to pay for a really-going-forward tsc counter. Signed-off-by:
Arjan van de Ven <arjan@linux.intel.com> Signed-off-by:
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Muli Ben-Yehuda authored
Spotted by d binderman <dcb314@hotmail.com>. Signed-off-by:
Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by:
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Andi Kleen authored
There is no guarantee that two RDTSCs in a row are monotonic, so don't assume it on single core AMD systems. This will make gettimeofday slower again Signed-off-by: -
Adrian Bunk authored
-mregparm=3 has been enabled by default for some time on i386, and AFAIK there aren't any problems with it left. This patch removes the REGPARM config option and sets -mregparm=3 unconditionally. Signed-off-by:
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Yinghai Lu authored
remove unused acpi_found_madt in mparse.c Signed-off-by:
Yinghai Lu <yinghai.lu@amd.com> Signed-off-by:
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Dave Jones authored
Sometimes the soft watchdog fires after we're done oopsing. See http://projects.info-pull.com/mokb/MOKB-25-11-2006.html for an example. AK: changed to touch_nmi_watchdog() Signed-off-by:
Dave Jones <davej@redhat.com> Signed-off-by:
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Rafael J. Wysocki authored
Make mce_remove_device() clean up the kobject in per_cpu(device_mce, cpu) after it has been unregistered. Signed-off-by:
Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by:
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Adrian Bunk authored
One ARCH_DISCONTIGMEM_ENABLE option is enough. Signed-off-by:
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Yinghai Lu authored
interrupt array is referred for idt vectors instead of NR_IRQS, so change size to NR_VECTORS - FIRST_EXTERNAL_VECTOR. Also change to static. Signed-off-by:
Yinghai Lu <yinghai@amd.com> Signed-off-by:
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Yinghai Lu authored
idt_table is in the .bss section, so clear_bss need to called at first Signed-off-by:
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Chuck Ebbert authored
Add sysctl for kstack_depth_to_print. This lets users change the amount of raw stack data printed in dump_stack() without having to reboot. Signed-off-by:
Chuck Ebbert <76306.1226@compuserve.com> Signed-off-by:
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Wink Saville authored
The comments for MSR_FS_BASE & MSR_GS_BASE were transposed. Signed-off-by:
Wink Saville <wink@saville.com> Signed-off-by:
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David Rientjes authored
Remove unused GET_APIC_VERSION call from clear_local_APIC() and __setup_APIC_LVTT(). Reported by D Binderman <dcb314@hotmail.com>. Cc: Andi Kleen <ak@suse.de> Cc: Ingo Molnar <mingo@redhat.com> Signed-off-by:
David Rientjes <rientjes@cs.washington.edu> Signed-off-by:
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Dave Jones authored
We do the exact same printk about a dozen lines above with no intermediate printk's. Signed-off-by:
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Artiom Myaskouvskey authored
When using memmap kernel parameter in EFI boot we should also add to memory map memory regions of runtime services to enable their mapping later. AK: merged and cleaned up the patch Signed-off-by:
Artiom Myaskouvskey <artiom.myaskouvskey@intel.com> Signed-off-by:
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Karsten Wiese authored
Read/Write APIC_LVTPC and APIC_LVTTHMR only, if get_maxlvt() returns certain values. This is done like everywhere else in i386/kernel/apic.c, so I guess its correct. Suspends/Resumes to disk fine and eleminates an smp_error_interrupt() here on a K8. AK: ported to x86-64 too Signed-off-by:
Karsten Wiese <fzu@wemgehoertderstaat.de> Signed-off-by:
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Andi Kleen authored
There are two consumers of apic=: the apic debug level and the low level generic architecture code. early_param would warn when the low level code rejected "debug". Avoid this. Signed-off-by: -
Stephane Eranian authored
Here is a small patch for i386 which adds a cpufeature flag and detection code for Intel's Branch Trace Store (BTS) feature. This feature can be found on Intel P4 and Core 2 processors among others. It can also be used by perfmon. changelog: - add CPU_FEATURE_BTS - add Branch Trace Store detection signed-off-by:
stephane eranian <eranian@hpl.hp.com> Signed-off-by:
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Stephane Eranian authored
Here is a small patch for x86-64 which adds a cpufeature flag and detection code for Intel's Branch Trace Store (BTS) feature. This feature can be found on Intel P4 and Core 2 processors among others. It can also be used by perfmon. changelog: - add CPU_FEATURE_BTS - add Branch Trace Store detection signed-off-by:
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Adrian Bunk authored
irq_vector[] can now become static. Signed-off-by:
Eric W. Biederman <ebiederm@xmission.com> Acked-by:
Ingo Molnar <mingo@redhat.com> Signed-off-by:
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Adrian Bunk authored
The Coverity checker noted that bad things might happen if find_isa_irq_apic() returned -1. [akpm@osdl.org: add debugging checks] Signed-off-by:
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Artiom Myaskouvskey authored
Function efi_get_time called not only during init kernel phase but also during suspend (from get_cmos_time). When it is called from get_cmos_time the corresponding runtime service should be called in virtual and not in physical mode. Signed-off-by:
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Siddha, Suresh B authored
Move the irqbalance quirks for E7320/E7520/E7525(Errata 23 in http://download.intel.com/design/chipsets/specupdt/30304203.pdf) to early quirks. And add a PCI quirk for these platforms to check(which happens very late during the boot) if the APIC routing is indeed set to default flat mode. This fixes the breakage(in x86_64) of this quirk due to cpu hotplug which selects physical mode instead of the logical flat(as needed for this errata workaround). Signed-off-by:
Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by:
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Siddha, Suresh B authored
Add genapic_force. Used by the next Intel quirks patch. Signed-off-by:
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Siddha, Suresh B authored
Change the 'no_control' field in the cpu struct to a more positive and better term 'hotpluggable'. And change(/cleanup) the logic accordingly. Signed-off-by:
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Siddha, Suresh B authored
Add 'enable_cpu_hotplug' flag and when cleared, the hotplug control file ("online") will not be added under /sys/devices/system/cpu/cpuX/ Next patch doing PCI quirks will use this. Signed-off-by: -
Siddha, Suresh B authored
Mechanism of selecting physical mode in genapic when cpu hotplug is enabled on x86_64, broke the quirk(quirk_intel_irqbalance()) introduced for working around the transposing interrupt message errata in E7520/E7320/E7525 (revision ID 0x9 and below. errata #23 in http://download.intel.com/design/chipsets/specupdt/30304203.pdf). This errata requires the mode to be in logical flat, so that interrupts can be directed to more than one cpu(and thus use hardware IRQ balancing enabled by BIOS on these platforms). Following four patches fixes this by moving the quirk to early quirk and forcing the x86_64 genapic selection to logical flat on these platforms. Thanks to Shaohua for pointing out the breakage. This patch: Add write_pci_config_byte() to direct PCI access routines Signed-off-by:
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