We already track if any phy inside the qmp wrapper has been initialized
by means of the struct qcom_qmp::init_count member. Let's drop the
duplicate 'initialized' member to simplify the code a bit.
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200916231202.3637932-4-swboyd@chromium.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>

The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the
wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy
structure to more accurately reflect what is going on. This also cleans
up 'struct qcom_qmp' so that it can eventually be the place where qmp
wrapper wide data is located, paving the way for the USB3+DP combo phy.
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200916231202.3637932-3-swboyd@chromium.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>

This binding only describes the USB phy inside the USB3 + DP "combo"
phy. Add information for the DP phy and describe the sub-nodes that
represent the DP and USB3 phys that exist inside the combo wrapper.
Remove reg-names from required properties because it isn't required nor
used by the kernel driver.
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: <devicetree@vger.kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200916231202.3637932-2-swboyd@chromium.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>

When WIZ wraps a Cadence Torrent PHY (instead of Cadence Sierra PHY)
there is a difference in the refclk-dig node: Torrent only has two
clocks instead of Sierra's four clocks. Add minItems: 2 to solve this.

Additionally, in our use case we only need to use assigned-clock for a
single clock, but the current binding requires either no assigned-clocks
or two. Fix this by adding minItems: 1 to all the assigned-clock
properties.

There was also an extra trailing whitespace, which this patch removes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Link: https://lore.kernel.org/r/20200918083743.213874-2-tomi.valkeinen@ti.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add reset-names as a required property.

There are no dts files using torrent phy yet, so it is safe to add a new
required property.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Link: https://lore.kernel.org/r/20200918083743.213874-1-tomi.valkeinen@ti.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Fix an implicit declaration of usleep_range():

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c: In function 'rk_dphy_enable':
drivers/phy/rockchip/phy-rockchip-dphy-rx0.c:203:2: error: implicit declaration of function 'usleep_range' [-Werror=implicit-function-declaration]

Fixes: 32abcc44 ("media: staging: phy-rockchip-dphy-rx0: add Rockchip MIPI Synopsys DPHY RX0 driver")
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20200921225618.52529-1-tfiga@chromium.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>

Fix a Kconfig warning that is causing lots of build errors
when USB_SUPPORT is not set.

USB_PHY depends on USB_SUPPORT but "select" doesn't care about
dependencies, so this driver should also depend on USB_SUPPORT.
It should not select USB_SUPPORT.

WARNING: unmet direct dependencies detected for USB_PHY
  Depends on [n]: USB_SUPPORT [=n]
  Selected by [m]:
  - USB_LGM_PHY [=m]
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Li Yin <yin1.li@intel.com>
Cc: Vadivel Murugan R <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/d1dd0ddd-3143-5777-1c63-195e1a32f237@infradead.orgSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add USB + SGMII/QSGMII multilink configuration sequences.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add PCIe + USB Unique SSC multilink configuration sequences.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add support for single link USB configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add support for single link SGMII/QSGMII configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Include PHY_PLL_CFG as a first register value to configure in
link_cmn_vals array values.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add support to configure link_cmn_vals and xcvr_diag_vals in case of single
link PHY configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Prepare and enable clock in probe instead of phy_init.
Also, remove phy_exit callback.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

For multilink configuration, deassert PHY and link reset after PHY
registers are configured in probe and only check link status in
power_on callback.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Added support for multilink configuration of Torrent PHY. Currently,
maximum two links are supported. In case of multilink configuration,
PHY needs to be configured for both the protocols simultaneously at
the beginning as per the requirement of Torrent PHY.
Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink
configurations are added.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add definition for QSGMII phy type.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1600327846-9733-5-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add support for PHY APB reset and make it optional.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Check if cmn_ready is set after both PLL0 and PLL1 are locked.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-3-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add single link PCIe register sequences in Torrent PHY driver.
Also, add support for getting SSC type from DT.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-2-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Torrent PHY can be used in different multi-link multi-protocol
configurations including protocols other than DisplayPort also,
such as PCIe, USB, SGMII, QSGMII etc. Update the bindings to have
support for these configurations.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-8-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add binding to specify Spread Spectrum Clocking mode used.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1600280911-9214-7-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add checking if total number of lanes for all subnodes is not greater than
number of lanes supported by PHY.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-6-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Added separate functions for regmap initialization of torrent PHY
generic registers and DP specific registers.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-5-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Enable support for multiple subnodes in torrent PHY to
include multi-link combinations.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-4-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Use devm_platform_ioremap_resource() to get register addresses instead of
boilerplate code.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-3-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Use of_device_get_match_data() to get driver data instead of boilerplate
code.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600280911-9214-2-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add support for eMMC PHY on Intel Keem Bay SoC.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200913235522.4316-4-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Binding description for Intel Keem Bay eMMC PHY.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200913235522.4316-3-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Rename phy-intel-{combo,emmc}.c to phy-intel-lgm-{combo,emmc}.c
to make drivers/phy/intel directory more generic for future use.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20200913235522.4316-2-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

The regmap_config structs are never modified and can be made const to
allow the compiler to put them in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200912204639.501669-4-rikard.falkeborn@gmail.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

cdns_nxp_sequence_pair[] are never modified and can be made const to allow
the compiler to put them in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Link: https://lore.kernel.org/r/20200912204639.501669-3-rikard.falkeborn@gmail.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

The static cdns_reg_pairs and regmap_config structs are not modified and
can be made const. This allows the compiler to put them in read-only
memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200912204639.501669-2-rikard.falkeborn@gmail.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Set Torrent PHY attributes bus_width, max_link_rate and mode
for DisplayPort.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1599805114-22063-3-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add new PHY attribute max_link_rate to struct phy_attrs. This indicates
maximum link rate supported by PHY (in Mbps).
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1599805114-22063-2-git-send-email-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add support for USB PHY on Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20200828022312.52724-3-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Add the dt-schema to support USB PHY on Intel LGM SoC
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200828022312.52724-2-vadivel.muruganx.ramuthevar@linux.intel.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

Move ti,omap-usb2 to its own YAML schema.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200831142130.21836-1-rogerq@ti.comSigned-off-by: Vinod Koul <vkoul@kernel.org>

On K3 AM654x/J721E platforms the Port MII mode selection register(s) have
similar format and placed in the System Control Module (SCM) module
sequentially as one register per port, but, depending SOC and CPSW
instance, the base offset and number of ports can be different.

Hence, add possibility to retrieve number of ports and base registers
offset from DT and support for max possible number of ports supported by K3
SoCs like J721E.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20200828201943.29155-4-grygorii.strashko@ti.comSigned-off-by: Vinod Koul <vkoul@kernel.org>