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  1. 02 May, 2019 1 commit
    • Tony Lindgren's avatar
      bus: ti-sysc: Handle devices with no control registers · e4f50c8d
      Tony Lindgren authored 
      Some interconnect target modules have no module control registers at
all, such as d_can on am335x and am437x.

The d_can register offset at 0 is CTL register with 0x401 as the default
value. I guess I mistook the 0x401 value for a revision register as the
value happens to look similar to what the revision registers typically
have for other modules.

To handle modules with no control registers, we need to improve the
ti-sysc driver a bit to bail out with errors on no control registers,
and then we can remove the bogus revision registers for d_can.

Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Tested-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      e4f50c8d
  3. 01 May, 2019 1 commit
    • Tony Lindgren's avatar
      ARM: dts: Configure osc clock for d_can on am335x · 516f1117
      Tony Lindgren authored 
      Reading the module revision register can cause an external abort on
non-linefetch depending of osc clock is not already enabled. This
started happening with commit 1a5cd7c2 ("bus: ti-sysc: Enable all
clocks directly during init to read revision") as reported by
Sebastian Andrzej Siewior <bigeasy@linutronix.de>.

The reason why the issue happens is because we now attempt to read the
interconnect target module revision register by first manually enabling
all the device clocks in sysc_probe(). And looks like d_can also needs
the osc clock in addition to the module clock, and it may or may not be
enabled depending on the bootloader version and if other devices have
already requested osc clock.

Let's fix the issue by adding osc clock as an optional clock for the
module for am335x. Note that am437x does not seem to list the osc clock
at all, so presumably it is not needed for am437x.

I also noticed that we're incorrectly assuming the revision register for
d_can exists. But the module does not seem to have any revision, sysconfig
or sysstatus registers. But that's mostly a cosmetic issues, so I'll send
a patch separately for that.

Fixes: 1a5cd7c2 ("bus: ti-sysc: Enable all clocks directly during init to read revision")
Reported-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Tested-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      516f1117
  5. 09 Apr, 2019 1 commit
  7. 08 Apr, 2019 17 commits
  9. 05 Apr, 2019 4 commits
  11. 03 Apr, 2019 6 commits
    • Tony Lindgren's avatar
      bus: ti-sysc: Add quirk handling for external optional functional clock · a54275f4
      Tony Lindgren authored 
      We cannot access mcpdm registers at all unless there is an optional pdmclk
configured. As this is currently only needed for mcpdm, let's check for
mcpdm in sysc_get_clocks(). If it turns out to be needed for other modules
too, we can add more flags to the quirks table for this.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      a54275f4
    • Tony Lindgren's avatar
      bus: ti-sysc: Add support for early quirks based on register address · 42b9c5c9
      Tony Lindgren authored 
      At least mcpdm needs an optional external clock enabled to function and
this clock typically comes from the PMIC. We can detect mcpdm based on
the interconnect target module address and set a quirk flag early.

To do this, let's initialize the clocks a bit later and add a new
function for sysc_init_early_quirks(). Note that we cannot yet enable
the early quirks for mcpdm until the optional external clocks are
handled in the in the following patch.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      42b9c5c9
    • Tony Lindgren's avatar
      bus: ti-sysc: Move rstctrl reset to happen later · b11c1ea1
      Tony Lindgren authored 
      We can do the rsstctrl a bit later, but need to deassert rstctrl reset
before the clocks are enabled if asserted. Let's only init restctrl
in sysc_init_resets() and do the reset later on just before we enable
the device clocks.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      b11c1ea1
    • Tony Lindgren's avatar
      bus: ti-sysc: Manage clocks for the interconnect target module in all cases · 93de83a2
      Tony Lindgren authored 
      We are currently not managing interconnect target module clocks in the
for legacy platform data based case. This causes a problem for using the
platform data based functions when dropping the platform data for the
interconnect target module configuration.

To avoid a situation where we need to populate the main and optional
clocks also for the platform data based functions, let's just manage the
clocks directly in ti-sysc driver. This means that until the interconnect
target module confugration platform data is dropped our use count for
clk_enable() will be 2 instead of 1.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      93de83a2
    • Tony Lindgren's avatar
      bus: ti-sysc: Allocate mdata as needed and do platform data based init later · a3e92e7b
      Tony Lindgren authored 
      The platform data based init functions typically reset the interconnect
target module configure the registers. As we may need the interconnect
target module specific quirks configured based on the revision register,
we want to move the platform data based init to happen later.

Let's allocate mdata as needed so it's available for sysc_legacy_init()
that we call with module clocks enabled from sysc_init_module().
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      a3e92e7b
    • Tony Lindgren's avatar
      bus: ti-sysc: Enable all clocks directly during init to read revision · 1a5cd7c2
      Tony Lindgren authored 
      The first thing we want to do is just read the module revision register to
be able to configure the module specific quirks and configure the module
registers.

As the interconnect target module may not yet be properly configured and
may need a reset first, we don't want to use pm_runtime_get() at this
point.

To read the revision register, let's just enable the all the clocks for
the interconnect target module during init even if the optional clocks
are not needed. That way we can read the revision register to configure
the quirks needed for PM runtime.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      1a5cd7c2
  13. 01 Apr, 2019 5 commits
  15. 26 Mar, 2019 5 commits
    • Tony Lindgren's avatar
      ARM: OMAP2+: Handle reset quirks for dynamically allocated modules · 8b30919a
      Tony Lindgren authored 
      For dynamically allocated struct omap_hwmod data, we need to populate
the device IP specific reset quirks.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      8b30919a
    • Tony Lindgren's avatar
      ARM: OMAP2+: Remove hwmod .rev data and use local SoC checks instead · 70451127
      Tony Lindgren authored 
      We can just check for omap2 and 3 for i2c and smartreflex locally.
The rest of the .rev data is already unused.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      70451127
    • Tony Lindgren's avatar
      ARM: OMAP2+: Allocate struct omap_hwmod based on dts data · b57250fa
      Tony Lindgren authored 
      With ti-sysc interconnect target module, we can allocate struct omap_hwmod
data based on the devicetree data. This allows dropping the static SoC
specific data eventually so we will only boot with data we actually need.

To allocate struct omap_hwmod dynamically, we need to add a mutex for
modifying the list, and remove __init for few functions.

Note that we are not initialized oh->_clk or the optional clocks and their
related quirks. That can be directly handled by the interconnect target
module driver.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      b57250fa
    • Tony Lindgren's avatar
      ARM: OMAP2+: Define _HWMOD_STATE_DEFAULT and use it · 6d63b12d
      Tony Lindgren authored 
      For dynamically allocated struct hwmod entries probing with ti-sysc
interconnect target module driver, we need to specify the initial default
state the same way as we do for the platform data cases.

Let's prepare for that by adding _HWMOD_STATE_DEFAULT that we can then
use to set the initial default state without a need to add similar
CONFIG_PM handling in multiple places.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      6d63b12d
    • Tony Lindgren's avatar
      ARM: OMAP2+: Prepare class allocation for dynamically allocated modules · 513a4abb
      Tony Lindgren authored 
      For dynamically allocated sysconfig data we only need to allocate a new
class for the cases where the class is shared. For dynamically allocated
struct omap_hwmod we will always allocate a new class.

Let's add detection for when we need to allocate a new class by comparing
the class name against the module name. If they match, there's no need
to allocate a new calls as we don't have case of mixed platform data and
dts data initialized modules for the same class.

Let's also move the init of class data inside the spinlock.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      513a4abb
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