Since we now have imx_timer structure, it makes more sense to move those
clock event related variables into the structure, so that we can save
some global variables.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Set up .set_next_event hook via imx_gpt_data, so that we can save the
use of timer_is_v2().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

It creates a gpt device speicific data structure and adds function hook
gpt_setup_tctl in there to set up gpt TCTL register.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Use different initialization function in CLOCKSOURCE_OF_DECLARE() to
initialize gpt device type for DT boot.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Define an enum for gpt timer device type in include/soc/imx/timer.h to
tell the gpt block differences among SoCs.  Update non-DT users (clock
drivers) to pass the device type.

As we now have include/soc/imx/timer.h, the declaration of
mxc_timer_init() is moved into there as the best fit.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Instead of passing around as individual argument, let's move timer
resources like irq and clocks together with base address into a data
structure, and pass pointer of the structure as argument to simplify
the function call interface.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed
which is endian-safe, as a step of moving the driver code into folder
drivers/clocksource.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

A recent change to the imx53 power management caused a build
regression when CONFIG_SOC_IMX53 is disabled:

mach-imx/built-in.o:(.init.rodata+0x60): undefined reference to `imx53_suspend'
mach-imx/built-in.o:(.init.rodata+0x64): undefined reference to `imx53_suspend_sz'

This avoids the problem by compiling the code in question
conditionally on the presence of CONFIG_SOC_IMX53. For
consistency, I'm also changing the same thing for
CONFIG_SOC_IMX51.

An additional benefit of this approach is reduced code size
for kernels that only include support for one of the two
SoCs.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 1579c7b9 ("ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

According to IMX6D/Q RM, table 18-3, sata clock's parent is ahb, not ipg.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add support for clock gating of I2C2 and I2C3.
We use I2C2 in a (not yet mainlined) device tree.
Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Use the generic mechanism to declare a bitmap instead of unsigned long.
Signed-off-by: Joe Perches <joe@perches.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add i.MX7D clk tree support.

Enable all clock to bring up imx7.
Clock framework need be modified a little since imx7d
change clock design. otherwise system will halt and block the
other part upstream.

All clock refine need wait for Dong Aisheng's patch
clk: support clocks which requires parent clock on during operation
Or other solution ready.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add type IMX_PLLV3_ENET_IMX7
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Enabled DAP (debug access port) by default. This enables the hw-
breakpoint framework to make use of the breakpoints and watchpoints
supported by hardware.

[    0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers.
[    0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes.

Without this clock, the hw-breakpoint driver claims an undefined
instruction during initialization:
[    0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
[    0.227519] hw-breakpoint: CPU 0 failed to disable vector catch
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

In order to save power the DDR pins should be put into high
impedance when in suspend to RAM.

This requires manually requesting self refresh (rather than using the
automatic mode implemented by the CCM / ESDCTL), followed by
reconfiguring the IOMUXC.

Of course the code to do this cannot itself run from DDR so the
code is copied to and executed from internal memory.

In my tests using a custom i.MX53 board with LPDDR2 RAM
this reduced the suspend power consumption from 200mW to 60mW.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add i.MX7D MSL support.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add low level uart debug support for imx7d
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Bai Ping <b51503@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Include the "common.h" header file to fix the following sparse warning:

arch/arm/mach-imx/mmdc.c:66:5: warning: symbol 'imx_mmdc_get_ddr_type' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Include the "clk.h" header file to fix the following sparse warning:

drivers/clk/imx/clk-cpu.c:77:12: warning: symbol 'imx_clk_cpu' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The comments were corrected as the following to reflect
the real situation of Freescale MXC timer IP block.
There are totally 4 version of the timer on Freescale i.MX SoCs.
Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Removed the duplicated function declaration of mxc_timer_init
which was already declared in drivers/clk/imx/clk.h.
Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The definition of do_div uses unsigned long long
variable as its first parameter, better to pass
a u64 variable as first parameter when calling
do_div function.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function")
moves imx6_set_lpm() from clock init function into
imx6_pm_common_init().  This causes a hang when cpuidle support is
enabled.  The reason for that is ARM core clock is shut down
unexpectedly by WAIT mode.  It happens with the following call stack:

    cpuidle_register_governor()
        cpuidle_switch_governor()
            cpuidle_uninstall_idle_handler()
                synchronize_sched()
                    wait_rcu_gp()
                        wait_for_completion()

When wait_for_completion() is called as above, all cores are idle/WFI.
Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a
hardware shutdown of the ARM core clock.

To fix the regression, we need to ensure that CCM_CLPCR_LPM is
initialized into RUN mode earlier than cpuidle governor registration,
which is a postcore_initcall.  This patch creates function
imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into
RUN mode, and have the function called from machine .init_irq hook,
which should be early enough.
Reported-by: Kevin Hilman <khilman@kernel.org>
Fixes: 8fb76a07 ("ARM: imx6: set initial power mode in pm function")
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

EPIT provides another timer implementation besides the default GPT
timer.  The imx35 clock driver will use EPIT timer when option
CONFIG_MXC_USE_EPIT is enabled.  However, initializing timers from
clock driver is a workaround solution and causes problem when we move
clock drivers into driver/clk.

Let's simply drop the EPIT initialization from there.  If people really
want this EPIT option, EPIT timer driver needs to be reworked to do the
initialization in a standard way - use CLOCKSOURCE_OF_DECLARE() with
device tree support.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add new created folders drivers/clk/imx/ and include/soc/imx/ into IMX
entry.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

After the cleanup on clock drivers, they are now ready to be moved into
drivers/clk.  Let's move them into drivers/clk/imx folder.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>

With the cleanup done before, we now can simply define base address and
irq as needed in clock driver, to get those platform header inclusions
removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Instead of calling cpu_is_xxx() in clk-pllv1 driver, let's add clk-pllv1
type support to handle the difference/quirk in particular SoC designs.
Doing so will help get clk-pllv1 driver ready for being moved out of
arch/arm/mach-imx folder.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

As we're about to move clock drivers out of arch/arm/mach-imx,
cpu_is_xxx() shouldn't be used any more.  Let's avoid the call by
looking at the device tree machine compatible string to determine
which SoC the clock driver is running on.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

We are about to move imx6 clock driver into drivers/clk, so let's get
imx6 pm code map CCM block on its own rather than relying on clock
driver to do the mapping.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Rather than setting initial low-power mode in every single i.MX6 clock
initialization function, we should really do that in pm code.  Let's
move imx6q_set_lpm(WAIT_CLOCKED) call into imx6_pm_common_init().

While at it, let's rename the function to imx6_set_lpm() since it's
actually common for all i.MX6 SoCs.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

We are about to move imx5 clock driver into drivers/clk, so let's get
imx5 pm code map CCM block on its own rather than relying on clock
driver to do the mapping.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The revision definitions and declarations are widely used by clock
drivers.  As a step of moving clock drivers out of arch/arm/mach-imx,
let's create header include/soc/imx/revision.h to accommodate them.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Replace the static mapping of CCM block in clock drivers with dynamic
mapping.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Pass physical address of timer block to mxc_timer_init() call, which in
turn does dynamic mapping within the function.  Thus, we can avoid using
static mapping in clock drivers.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

It adds the imx7d clock ID definitions which will be used by both imx7d
clock driver and device tree.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

AMD CPUs don't reinitialize the SS descriptor on SYSRET, so SYSRET with
SS == 0 results in an invalid usermode state in which SS is apparently
equal to __USER_DS but causes #SS if used.

Work around the issue by setting SS to __KERNEL_DS __switch_to, thus
ensuring that SYSRET never happens with SS set to NULL.

This was exposed by a recent vDSO cleanup.

Fixes: e7d6eefa x86/vdso32/syscall.S: Do not load __USER32_DS to %ss
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Cc: Peter Anvin <hpa@zytor.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Denys Vlasenko <vda.linux@googlemail.com>
Cc: Brian Gerst <brgerst@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Pull intel drm fixes from Dave Airlie.

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/i915: vlv: fix save/restore of GFX_MAX_REQ_COUNT reg
  drm/i915: Workaround to avoid lite restore with HEAD==TAIL
  drm/i915: cope with large i2c transfers