1. 14 Apr, 2015 7 commits
  2. 02 Apr, 2015 7 commits
    • Paul Walmsley's avatar
      ARM: 8335/1: Documentation: DT bindings: Tegra AHB: document the legacy base address · 38e42f12
      Paul Walmsley authored
      Documentation: DT bindings: Tegra AHB: require the legacy base address for existing chips
      
      Per Stephen Warren, note in the Tegra AHB DT binding documentation
      that we specifically deprecate any attempt to use the IP block's
      actual hardware base address, and advocate the use of the legacy
      "off-by-four" address in the 'regs' property, for Tegra chips with
      existing upstream Linux DT files that include a Tegra AHB node.  This
      patch updates the documentation accordingly.
      
      Changing the existing kernel DT data isn't under consideration because
      Linux kernel DT data policy is to preserve compatibility between newer
      DT data files and older kernels.  However, this additional step of
      changing the documentation should discourage others from sending
      kernel patches to try to change the legacy kernel DT data.
      Furthermore, for out-of-tree software (such as bootloaders or other
      operating systems) that may rely on Linux kernel DT binding
      documentation as an ABI (but not the Linux kernel DT data itself),
      such a change may allow future convergence with the Linux kernel DT
      data without additional code changes.
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: Eduardo Valentin <edubezval@gmail.com>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Acked-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      38e42f12
    • Paul Walmsley's avatar
      ARM: 8334/1: amba: tegra-ahb: detect and correct bogus base address · ce7a10b0
      Paul Walmsley authored
      amba: tegra-ahb: detect and correct bogus base address
      
      From a hardware SoC integration point of view, the starting address of
      this IP block in the existing Tegra SoC DT files is off by 4 bytes
      from the actual base address.  Since we attempt to make old DT files
      forward-compatible with newer kernels, we cannot fix the IP block base
      address in old DT data. This patch works around the problem by
      detecting the four byte base address offset in the driver code, and
      correcting it if it's detected.  (In general, IP block base addresses
      almost always have a null low byte.)
      
      Future SoC DT data for Tegra AHB should use the correct Tegra AHB base
      address, in cases where there is no DT data backward compatibility
      requirement.
      
      This patch is a revision of the patch originally titled
      "amba: tegra-ahb: use correct base address for future chip support".
      This revision implements changes requested by Russell King:
      
      http://marc.info/?l=linux-tegra&m=142658851825062&w=2
      http://marc.info/?l=linux-tegra&m=142658873925178&w=2Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: Hiroshi DOYU <hdoyu@nvidia.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: linux-kernel@vger.kernel.org
      Acked-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ce7a10b0
    • Paul Walmsley's avatar
      ARM: 8333/1: amba: tegra-ahb: fix register offsets in the macros · 049e4b3f
      Paul Walmsley authored
      amba: tegra-ahb: fix register offsets in the macros
      
      From a hardware SoC integration point of view, the offsets of the
      Tegra AHB registers that are currently defined in tegra-ahb.c macros
      are all off by four bytes.  Similarly, the starting address of this IP
      block in our existing DT files is also off by four bytes.  Since we
      attempt to make old DT files forward-compatible with newer kernels, we
      cannot fix the IP block base address in old DT data.  However, we can
      fix the offsets in the driver so that they are correct with respect to
      the hardware, which is what this patch does.  And a subsequent patch
      will allow the offset to be removed for DT 'compatible' strings used
      in future DT files for newer Tegra chips that the kernel does not yet
      support.
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: Hiroshi DOYU <hdoyu@nvidia.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: linux-kernel@vger.kernel.org
      Acked-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      049e4b3f
    • Geert Uytterhoeven's avatar
      ARM: 8339/1: Enable CONFIG_GENERIC_IRQ_SHOW_LEVEL · 7c07005e
      Geert Uytterhoeven authored
      Several interrupt controllers support both edge and level interrupts, so
      it's useful to provide that information in /proc/interrupts.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      7c07005e
    • Geert Uytterhoeven's avatar
      ARM: 8338/1: kexec: Relax SMP validation to improve DT compatibility · fee3fd4f
      Geert Uytterhoeven authored
      When trying to kexec into a new kernel on a platform where multiple CPU
      cores are present, but no SMP bringup code is available yet, the
      kexec_load system call fails with:
      
          kexec_load failed: Invalid argument
      
      The SMP test added to machine_kexec_prepare() in commit 2103f6cb
      ("ARM: 7807/1: kexec: validate CPU hotplug support") wants to prohibit
      kexec on SMP platforms where it cannot disable secondary CPUs.
      However, this test is too strict: if the secondary CPUs couldn't be
      enabled in the first place, there's no need to disable them later at
      kexec time.  Hence skip the test in the absence of SMP bringup code.
      
      This allows to add all CPU cores to the DTS from the beginning, without
      having to implement SMP bringup first, improving DT compatibility.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Acked-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      fee3fd4f
    • Russell King's avatar
      ARM: move reboot code to arch/arm/kernel/reboot.c · 045ab94e
      Russell King authored
      Move shutdown and reboot related code to a separate file, out of
      process.c.  This helps to avoid polluting process.c with non-process
      related code.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      045ab94e
    • Russell King's avatar
      ARM: fix broken hibernation · 767bf7e7
      Russell King authored
      Normally, when a CPU wants to clear a cache line to zero in the external
      L2 cache, it would generate bus cycles to write each word as it would do
      with any other data access.
      
      However, a Cortex A9 connected to a L2C-310 has a specific feature where
      the CPU can detect this operation, and signal that it wants to zero an
      entire cache line.  This feature, known as Full Line of Zeros (FLZ),
      involves a non-standard AXI signalling mechanism which only the L2C-310
      can properly interpret.
      
      There are separate enable bits in both the L2C-310 and the Cortex A9 -
      the L2C-310 needs to be enabled and have the FLZ enable bit set in the
      auxiliary control register before the Cortex A9 has this feature
      enabled.
      
      Unfortunately, the suspend code was not respecting this - it's not
      obvious from the code:
      
      swsusp_arch_suspend()
       cpu_suspend() /* saves the Cortex A9 auxiliary control register */
        arch_save_image()
        soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
         cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
      
      At this point, we end up with the L2C disabled, but the Cortex A9 with
      FLZ enabled - which means any memset() or zeroing of a full cache line
      will fail to take effect.
      
      A similar issue exists in the resume path, but it's slightly more
      complex:
      
      swsusp_arch_suspend()
       cpu_suspend() /* saves the Cortex A9 auxiliary control register */
        arch_save_image() /* image with A9 auxcr saved */
      ...
      swsusp_arch_resume()
       call_with_stack()
        arch_restore_image() /* restores image with A9 auxcr saved above */
        soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
         cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
      
      Again, here we end up with the L2C disabled, but Cortex A9 FLZ enabled.
      
      There's no need to turn off the L2C in either of these two paths; there
      are benefits from not doing so - for example, the page copies will be
      faster with the L2C enabled.
      
      Hence, fix this by providing a variant of soft_restart() which can be
      used without turning the L2 cache controller off, and use it in both
      of these paths to keep the L2C enabled across the respective resume
      transitions.
      
      Fixes: 8ef418c7 ("ARM: l2c: trial at enabling some Cortex-A9 optimisations")
      Reported-by: default avatarSean Cross <xobs@kosagi.com>
      Tested-by: default avatarSean Cross <xobs@kosagi.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      767bf7e7
  3. 29 Mar, 2015 7 commits
  4. 28 Mar, 2015 6 commits
  5. 27 Mar, 2015 1 commit
  6. 18 Mar, 2015 1 commit
  7. 10 Mar, 2015 1 commit
  8. 24 Feb, 2015 1 commit
  9. 23 Feb, 2015 6 commits
    • Carlo Caione's avatar
      ARM: 8304/1: Respect NO_KERNEL_MAPPING when we don't have an IOMMU · 6e8266e3
      Carlo Caione authored
      Even without an iommu, NO_KERNEL_MAPPING is still convenient to save on
      kernel address space in places where we don't need a kernel mapping.
      Implement support for it in the two places where we're creating an
      expensive mapping.
      
      __alloc_from_pool uses an internal pool from which we already have
      virtual addresses, so it's not relevant, and __alloc_simple_buffer uses
      alloc_pages, which will always return a lowmem page, which is already
      mapped into kernel space, so we can't prevent a mapping for it in that
      case.
      Signed-off-by: default avatarJasper St. Pierre <jstpierre@mecheye.net>
      Signed-off-by: default avatarCarlo Caione <carlo@caione.org>
      Reviewed-by: default avatarRob Clark <robdclark@gmail.com>
      Reviewed-by: default avatarDaniel Drake <dsd@endlessm.com>
      Acked-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      6e8266e3
    • Lorenzo Pieralisi's avatar
      ARM: 8293/1: kernel: fix pci_mmap_page_range() offset calculation · 415ae101
      Lorenzo Pieralisi authored
      The pci_mmap_page_range() API should be written to expect offset
      values representing PCI memory resource addresses as seen by user
      space, through the pci_resource_to_user() API.
      
      ARM relies on the standard implementation of pci_resource_to_user()
      which actually is an identity map and exports to user space
      PCI memory resources as they are stored in PCI devices resources
      structures, which represent CPU physical addresses (fixed-up using
      BUS to CPU address conversions) not PCI bus addresses.
      
      Therefore, on ARM platforms where the mapping between CPU and BUS
      address is not a 1:1 the current pci_mmap_page_range() implementation is
      erroneous, in that an additional shift is applied to an already fixed-up
      offset passed from userspace.
      
      Hence, this patch removes the mem_offset from the pgoff calculation
      since the offset as passed from user space already represents the CPU
      physical address corresponding to the resource to be mapped, ie no
      additional offset should be applied.
      
      Cc: Arnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      415ae101
    • Ard Biesheuvel's avatar
      ARM: 8219/1: handle interworking and out-of-range relocations separately · 2b8514d0
      Ard Biesheuvel authored
      Currently, interworking calls on module boundaries are not supported,
      and are handled by the same error handling code path as non-interworking
      calls whose targets are simply out of range.
      
      Before modifying the handling of those out-of-range jump and call
      relocations in a subsequent patch, move the handling of interworking
      restrictions out of it.
      Acked-by: default avatarNicolas Pitre <nico@linaro.org>
      Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      2b8514d0
    • Linus Torvalds's avatar
      Linux 4.0-rc1 · c517d838
      Linus Torvalds authored
      .. after extensive statistical analysis of my G+ polling, I've come to
      the inescapable conclusion that internet polls are bad.
      
      Big surprise.
      
      But "Hurr durr I'ma sheep" trounced "I like online polls" by a 62-to-38%
      margin, in a poll that people weren't even supposed to participate in.
      Who can argue with solid numbers like that? 5,796 votes from people who
      can't even follow the most basic directions?
      
      In contrast, "v4.0" beat out "v3.20" by a slimmer margin of 56-to-44%,
      but with a total of 29,110 votes right now.
      
      Now, arguably, that vote spread is only about 3,200 votes, which is less
      than the almost six thousand votes that the "please ignore" poll got, so
      it could be considered noise.
      
      But hey, I asked, so I'll honor the votes.
      c517d838
    • Linus Torvalds's avatar
      Merge tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4 · feaf2229
      Linus Torvalds authored
      Pull ext4 fixes from Ted Ts'o:
       "Ext4 bug fixes.
      
        We also reserved code points for encryption and read-only images (for
        which the implementation is mostly just the reserved code point for a
        read-only feature :-)"
      
      * tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
        ext4: fix indirect punch hole corruption
        ext4: ignore journal checksum on remount; don't fail
        ext4: remove duplicate remount check for JOURNAL_CHECKSUM change
        ext4: fix mmap data corruption in nodelalloc mode when blocksize < pagesize
        ext4: support read-only images
        ext4: change to use setup_timer() instead of init_timer()
        ext4: reserve codepoints used by the ext4 encryption feature
        jbd2: complain about descriptor block checksum errors
      feaf2229
    • Linus Torvalds's avatar
      Merge branch 'for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs · be5e6616
      Linus Torvalds authored
      Pull more vfs updates from Al Viro:
       "Assorted stuff from this cycle.  The big ones here are multilayer
        overlayfs from Miklos and beginning of sorting ->d_inode accesses out
        from David"
      
      * 'for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (51 commits)
        autofs4 copy_dev_ioctl(): keep the value of ->size we'd used for allocation
        procfs: fix race between symlink removals and traversals
        debugfs: leave freeing a symlink body until inode eviction
        Documentation/filesystems/Locking: ->get_sb() is long gone
        trylock_super(): replacement for grab_super_passive()
        fanotify: Fix up scripted S_ISDIR/S_ISREG/S_ISLNK conversions
        Cachefiles: Fix up scripted S_ISDIR/S_ISREG/S_ISLNK conversions
        VFS: (Scripted) Convert S_ISLNK/DIR/REG(dentry->d_inode) to d_is_*(dentry)
        SELinux: Use d_is_positive() rather than testing dentry->d_inode
        Smack: Use d_is_positive() rather than testing dentry->d_inode
        TOMOYO: Use d_is_dir() rather than d_inode and S_ISDIR()
        Apparmor: Use d_is_positive/negative() rather than testing dentry->d_inode
        Apparmor: mediated_filesystem() should use dentry->d_sb not inode->i_sb
        VFS: Split DCACHE_FILE_TYPE into regular and special types
        VFS: Add a fallthrough flag for marking virtual dentries
        VFS: Add a whiteout dentry type
        VFS: Introduce inode-getting helpers for layered/unioned fs environments
        Infiniband: Fix potential NULL d_inode dereference
        posix_acl: fix reference leaks in posix_acl_create
        autofs4: Wrong format for printing dentry
        ...
      be5e6616
  10. 22 Feb, 2015 3 commits