1. 17 Feb, 2015 2 commits
  2. 05 Feb, 2015 4 commits
  3. 26 Jan, 2015 6 commits
  4. 23 Jan, 2015 4 commits
  5. 22 Jan, 2015 2 commits
  6. 14 Jan, 2015 3 commits
  7. 13 Jan, 2015 6 commits
    • Arnaud Ebalard's avatar
      dt-bindings: use isil prefix for Intersil in I2C trivial-devices.txt · ef282914
      Arnaud Ebalard authored
      This patch fixes I2C trivial-devices.txt DT documentation file to
      reference isil (NASDAQ symbol and the most used prefix inside the
      kernel) for Intersil.
      
      It reverts 7c75c1d5 ("dt-bindings: Document deprecated device
      vendor name to fix related warning").
      Signed-off-by: default avatarArnaud Ebalard <arno@natisbad.org>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      ef282914
    • Nicholas Mc Guire's avatar
      i2c: imx: fix handling of wait_for_completion_timeout result · cb9eaba4
      Nicholas Mc Guire authored
      wait_for_completion_timeout does not return negative values so
      "result" handling here should be simplified to cover the actually
      possible cases only.
      Signed-off-by: default avatarNicholas Mc Guire <der.herr@hofr.at>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      cb9eaba4
    • Doug Anderson's avatar
      i2c: rk3x: Account for repeated start time requirement · 387f0de6
      Doug Anderson authored
      On Rockchip I2C the controller drops SDA low slightly too soon to meet
      the "repeated start" requirements.
      
      >From my own experimentation over a number of rates:
       - controller appears to drop SDA at .875x (7/8) programmed clk high.
       - controller appears to keep SCL high for 2x programmed clk high.
      
      The first rule isn't enough to meet tSU;STA requirements in
      Standard-mode on the system I tested on.  The second rule is probably
      enough to meet tHD;STA requirements in nearly all cases (especially
      after accounting for the first), but it doesn't hurt to account for it
      anyway just in case.
      
      Even though the repeated start requirement only need to be accounted
      for during a small part of the transfer, we'll adjust the timings for
      the whole transfer to meet it.  I believe that adjusting the timings
      in just the right place to switch things up for repeated start would
      require several extra interrupts and that doesn't seem terribly worth
      it.
      
      With this change and worst case rise/fall times, I see 100kHz i2c
      going to ~85kHz.  With slightly optimized rise/fall (800ns / 50ns) I
      see i2c going to ~89kHz.  Fast-mode isn't affected much because
      tSU;STA is shorter relative to tHD;STA there.
      
      As part of this change we needed to account for the SDA falling time.
      The specification indicates that this should be the same, but we'll
      follow Designware's lead and add a binding.  Note that we deviate from
      Designware and assign the default SDA falling time to be the same as
      the SCL falling time, which is incredibly likely.
      Signed-off-by: default avatarDoug Anderson <dianders@chromium.org>
      [wsa: rebased to i2c/for-next]
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      387f0de6
    • addy ke's avatar
      i2c: rk3x: fix bug that cause measured high_ns doesn't meet I2C specification · 1330e291
      addy ke authored
      The number of clock cycles to be written into the CLKDIV register
      that determines the I2C clk high phase includes the rise time.
      So to meet the timing requirements defined in the I2C specification
      which defines the minimal time SCL has to be high, the rise time
      has to taken into account. The same applies to the low phase with
      falling time.
      
      In my test on RK3288-Pink2 board, which is not an upstream board yet,
      if external pull-up resistor is 4.7K, rise_ns is about 700ns.
      So the measured high_ns is about 3900ns, which is less than 4000ns
      (the minimum high_ns in I2C specification for Standard-mode).
      
      To fix this bug min_low_ns should include fall time and min_high_ns
      should include rise time.
      
      This patch merged the patch from chromium project which can get the
      rise and fall times for signals from the device tree. This allows us
      to more accurately calculate timings. see:
      https://chromium-review.googlesource.com/#/c/232774/Signed-off-by: default avatarAddy Ke <addy.ke@rock-chips.com>
      Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
      Tested-by: default avatarDoug Anderson <dianders@chromium.org>
      [wsa: fixed a typo in the docs]
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      1330e291
    • Harini Katakam's avatar
      i2c: cadence: Handle > 252 byte transfers · 9fae82e1
      Harini Katakam authored
      The I2C controller sends a NACK to the slave when transfer size register
      reaches zero, irrespective of the hold bit. So, in order to handle transfers
      greater than 252 bytes, the transfer size register has to be maintained at a
      value >= 1. This patch implements the same.
      The interrupt status is cleared at the beginning of the isr instead of
      the end, to avoid missing any interrupts.
      Signed-off-by: default avatarHarini Katakam <harinik@xilinx.com>
      [wsa: added braces around else branch]
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      9fae82e1
    • Wolfram Sang's avatar
      i2c: pmcmsp: remove dead code · 1c574993
      Wolfram Sang authored
      CPPCHECK rightfully says:
      
      drivers/i2c/busses/i2c-pmcmsp.c:151: style: The function 'pmcmsptwi_reg_to_clock' is never used.
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      1c574993
  8. 22 Dec, 2014 1 commit
    • Lars-Peter Clausen's avatar
      i2c: Remove support for legacy PM · 523c5b89
      Lars-Peter Clausen authored
      There haven't been any I2C driver that use the legacy suspend/resume
      callbacks for a while now and new drivers are supposed to use PM ops. So
      remove support for legacy suspend/resume for I2C drivers.
      
      Since there aren't any special bus specific things to do during
      suspend/resume and since the PM core will automatically fallback directly to
      using the device's PM ops if no bus PM ops are specified there is no need to
      have any I2C bus PM ops.
      Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      523c5b89
  9. 21 Dec, 2014 3 commits
    • Linus Torvalds's avatar
      Linux 3.19-rc1 · 97bf6af1
      Linus Torvalds authored
      97bf6af1
    • Linus Torvalds's avatar
      Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux · 60815cf2
      Linus Torvalds authored
      Pull ACCESS_ONCE cleanup preparation from Christian Borntraeger:
       "kernel: Provide READ_ONCE and ASSIGN_ONCE
      
        As discussed on LKML http://marc.info/?i=54611D86.4040306%40de.ibm.com
        ACCESS_ONCE might fail with specific compilers for non-scalar
        accesses.
      
        Here is a set of patches to tackle that problem.
      
        The first patch introduce READ_ONCE and ASSIGN_ONCE.  If the data
        structure is larger than the machine word size memcpy is used and a
        warning is emitted.  The next patches fix up several in-tree users of
        ACCESS_ONCE on non-scalar types.
      
        This does not yet contain a patch that forces ACCESS_ONCE to work only
        on scalar types.  This is targetted for the next merge window as Linux
        next already contains new offenders regarding ACCESS_ONCE vs.
        non-scalar types"
      
      * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux:
        s390/kvm: REPLACE barrier fixup with READ_ONCE
        arm/spinlock: Replace ACCESS_ONCE with READ_ONCE
        arm64/spinlock: Replace ACCESS_ONCE READ_ONCE
        mips/gup: Replace ACCESS_ONCE with READ_ONCE
        x86/gup: Replace ACCESS_ONCE with READ_ONCE
        x86/spinlock: Replace ACCESS_ONCE with READ_ONCE
        mm: replace ACCESS_ONCE with READ_ONCE or barriers
        kernel: Provide READ_ONCE and ASSIGN_ONCE
      60815cf2
    • Linus Torvalds's avatar
      Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux · bfc7249c
      Linus Torvalds authored
      Pull clk framework updates from Mike Turquette:
       "This is much later than usual due to several last minute bugs that had
        to be addressed.  As usual the majority of changes are new drivers and
        modifications to existing drivers.  The core recieved many fixes along
        with the groundwork for several large changes coming in the future
        which will better parition clock providers from clock consumers"
      
      * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
        clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
        ARM: OMAP3: clock: fix boot breakage in legacy mode
        ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
        clk: Really fix deadlock with mmap_sem
        clk: mmp: fix sparse non static symbol warning
        clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
        clk: change clk_debugfs_add_file to take a struct clk_hw
        clk: Don't expose __clk_get_accuracy
        clk: Don't try to use a struct clk* after it could have been freed
        clk: Remove unused function __clk_get_prepare_count
        clk: samsung: Fix double add of syscore ops after driver rebind
        clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
        clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
        clk: samsung: remove unnecessary inclusion of header files from clk.h
        clk: samsung: remove unnecessary CONFIG_OF from clk.c
        clk: samsung: Spelling s/bwtween/between/
        clk: rockchip: Add support for the mmc clock phases using the framework
        clk: rockchip: add bindings for the mmc clocks
        clk: rockchip: rk3288 export i2s0_clkout for use in DT
        clk: rockchip: use clock ID for DMC (memory controller) on rk3288
        ...
      bfc7249c
  10. 20 Dec, 2014 9 commits