- 30 Aug, 2022 13 commits
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Hawking Zhang authored
Add ip block support for mes v11_0_3. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Add ip block support for gfx v11_0_3. Signed-off-by:
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Hawking Zhang authored
Set AMDGPU_FAMILY_GC_11_0_0. Signed-off-by:
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Hawking Zhang authored
All gc v11_0_3 registers in gcvml2 range have different register offset from the ones in gc v11_0_0. v11_0_3 imu_rlc_ram programming has to be separated from v11_0_0 implementation v2: fix checkpatch errors (Alex) Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
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David Belanger authored
Added missing cases for GFX 11.0.3 code in a few switch statements. Signed-off-by:
David Belanger <david.belanger@amd.com> Reviewed-by:
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Hawking Zhang authored
initialize some gfx config for gfx v11_0_3 Signed-off-by:
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Hawking Zhang authored
To support new mes ip block Signed-off-by:
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Hawking Zhang authored
To support new gfx ip block Signed-off-by:
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Hawking Zhang authored
Add ip block support for gmc v11_0_3. Signed-off-by:
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Hawking Zhang authored
initialize gmc sw config for v11_0_3 Signed-off-by:
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Yang Wang authored
add gfxhub_v3_0_3 support Signed-off-by:
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Frank Min authored
Add gc v11_0_3 register offset and shift masks header files v2: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
Not all the gfx10 variants need to integrate global tap_delay and per se tap_delay firmwares Only init tap_delay ucode when it does include in rlc ucode binary so driver doesn't send a null buffer to psp for firmware loading Signed-off-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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- 29 Aug, 2022 27 commits
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Yang Li authored
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yang Li authored
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891Reported-by:
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Yang Li authored
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886Reported-by:
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Yang Li authored
1. The indentation of statements in the same curly bracket should be consistent. 2. Variable declarations in the same function should be aligned. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1889Reported-by:
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Hawking Zhang authored
Add ip block support for lsdma v6_0_3. Signed-off-by:
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Hawking Zhang authored
Add ip block support for sdma v6_0_3. Signed-off-by:
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Hawking Zhang authored
To support new sdma ip block Signed-off-by:
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John Clements authored
Force to enable smu block for SMU v13.0.10 Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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John Clements authored
added sw pptable id 6666 for smu 13.0.10 v2: fix checkpatch error (Alex) Signed-off-by:
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Yang Wang authored
add smu_v13_0_10 driver if version Signed-off-by:
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Yang Wang authored
add smu_v13_0_10 support. Signed-off-by:
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Frank Min authored
Add ip block support for psp v13_0_10. Signed-off-by:
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John Clements authored
added missing firmware module Signed-off-by:
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Frank Min authored
Add psp v13_0_10 ip block, initialize firmware and psp functions Signed-off-by:
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Hawking Zhang authored
Add ip block support for soc21_common. Signed-off-by:
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Sonny Jiang authored
This enable VCN PG, CG, DPG and JPEG PG, CG Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
init cp/pg_flags and extenal_rev_id Signed-off-by:
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Hawking Zhang authored
driver doesn't need to program any gc 11_0_0 golden Signed-off-by:
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Jinpeng Cui authored
Return value from kfd_wait_on_events() and io_remap_pfn_range() directly instead of taking this in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Jinpeng Cui <cui.jinpeng2@zte.com.cn> Signed-off-by:
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Jinpeng Cui authored
Return value from expression directly instead of taking this in another redundant variable. Reported-by:
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Martin Tsai authored
[Why] Incorrect cursor position will induce system hang on pipe split. [How] 1.Handle horizontal mirror on rotation, 2.Correct cursor set on piep split. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Vladimir Stempen authored
[Why] On secondary display hotplug we switch primary stream from ODM2to1 to ODMBypass mode. Current logic will trigger disabling front end for this stream. [How] We need to check if prev_odm_pipe is equal to NULL in order to disable dangling planes in this scenario. Reviewed-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by:
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Ethan Wellenreiter authored
[WHY] Function wasn't returning false when it had a no stream [HOW] Made it return false when it had no stream. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by:
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Ethan Wellenreiter authored
[Why] Pipes get merged in preparation for SubVP but if they don't get used, and are in ODM or some other multi pipe config, it would calculate the voltage level with a viewport of just one pipe from when they were split resulting in too low of a voltage level. [How] Made it so that the viewport and other timing settings get rebuilt and re- initialized after the pipe merge, before calculating the voltage level so it would calculate it correctly. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] plane and stream variables used for cursor size allocation calculation were stale from previous iteration. Redo the iteration to find the correct cursor plane for the calculation. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Alex Sierra authored
[Why] Devices with CPU XGMI iolink do not support PCIe peer access. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aric Cyr authored
Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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