- 13 Sep, 2022 40 commits
-
-
Nicholas Kazlauskas authored
[Why] HW can support the display swizzle modes for video, and those are preferable over standard or linear for decode use. [How] Remove the check for DCN314. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Nicholas Kazlauskas authored
[Why & How] Add support for the DML314 functions and hook up DCN314 to use them. This has some necessary additions for calculating Max VSTARTUP for future features, but there's also some changes that we have to make for pixel format/swizzle support. That will come in a following patch to make this transition easier to bisect. Tested-by:
-
Rodrigo Siqueira authored
We were not using the VBA and DLG files for DCN314, but the next sequence of changes for DCN314 will require those files. This commit adds the necessary files to the Makefile. Cc: Roman Li <roman.li@amd.com> Tested-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
-
Rodrigo Siqueira authored
We have some compilation errors in some DML files from DCN314 that we never noticed because we were not compiling some of the DML files. This commit fixes those syntax errors before we enable the compilation. Cc: Roman Li <roman.li@amd.com> Tested-by:
-
Aric Cyr authored
[why] Incorrectly using MicroTileWidth instead of MacroTileWidth for calculations. [how] Remove all unused references to MicroTile and change them to MacroTile. Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
-
Leo Chen authored
[Why & How] DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software. Removed all instances of resetting the register to 0 Tested-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] Leverage SW cursor fall back for SubVP when the cursor is too big. We want to take advantage of being able to fallback to SW cursor when possible because it's not worth it to disable MCLK switching because the cursor is slightly too big. Tested-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by:
-
JinZe.Xu authored
[Why] link type is not assigned before check dpia_mst_dsc_always_on conditions. Tested-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
-
Nagulendran, Iswara authored
[HOW&WHY] Revert a previous commit by moving DSC programming back to before link enablement. Tested-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Acked-by:
Nagulendran, Iswara <Iswara.Nagulendran@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] Update MBLK calculation according to hardware doc. For DCC case we were not allocation enough MALL due to an inaccurate MBLK calculation. Tested-by:
-
Aurabindo Pillai authored
This reverts commit a4f1b042 since returning false in case of SubVP results in no cursor being visible on desktop as there is no sw cursor fallback path on all platforms. Tested-by:
-
Chris Park authored
[Why] I2C register name starts with 1, unlike other registers that start with 0. This creates a problem with the new register macro refactoring when I2C HW objects are created in an array. [How] Correct I2C register offset by making a new macro to account for array offset. Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Signed-off-by:
-
Aric Cyr authored
[why] Conditionals in the DML basic math functions significantly impact mode enumeration. [how] Remove conditionals for floor/ceil operations which are used frequently in DML and add an assertion for invalid callers using zero granuality. Fix existing callers that rely on 0 granularity. Tested-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
-
Candice Li authored
No need to reset error status since only umc ras supported on psp v13_0_0. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Candice Li authored
Set correct EEPROM I2C address for smu v13_0_0. Signed-off-by:
-
John Clements authored
copy ras driver to psp if present Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by:
-
Alex Deucher authored
Was missing before and would have resulted in a write to a non-existant register. Normally APUs don't use HDP, but other asics could use this code and APUs do use the HDP when used in passthrough. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
-
Jingyu Wang authored
Remove "default n" options. If the "default" line is removed, it defaults to 'n'. Signed-off-by:
Jingyu Wang <jingyuwang_vip@163.com> Signed-off-by:
-
Jilin Yuan authored
Delete the redundant word 'in'. Signed-off-by:
Jilin Yuan <yuanjilin@cdjrlc.com> Signed-off-by:
-
Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_amdkfd_gpuvm.c Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_amdkfd.c Signed-off-by:
-
Jingyu Wang authored
This is a patch to the amdgpu_sync.c file that fixes some warnings found by the checkpatch.pl tool Signed-off-by:
-
Jingyu Wang authored
Fix everything checkpatch.pl complained about in amdgpu_acpi.c Signed-off-by:
-
zhang songyi authored
Return the sdma_v6_0_start() directly instead of storing it in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
zhang songyi <zhang.songyi@zte.com.cn> Signed-off-by:
-
ye xingchen authored
Return the value radeon_drm_ioctl() directly instead of storing it in another redundant variable. Reported-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
-
ye xingchen authored
Return the value ci_load_smc_ucode() directly instead of storing it in another redundant variable. Reported-by:
-
Yang Li authored
Conditional statements have no effect to next process.So remove it. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2028Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
-
Yang Li authored
The result of relational operation is Boolean, and the question mark expression is redundant. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2027Reported-by:
-
Yang Li authored
This if statement is the content of the for statement above it. It should be indented. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2026Reported-by:
-
Vignesh Chander authored
both get_xgmi_hive and put_xgmi_hive can be skipped since the reset domain is not necessary for VF Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by:
-
Philip Yang authored
migrate_vma_setup shows below warning because we don't hold another process mm mmap_lock. We should use current vmf->vma->vm_mm instead, the caller already hold current mmap lock inside CPU page fault handler. WARNING: CPU: 10 PID: 3054 at include/linux/mmap_lock.h:155 find_vma Call Trace: walk_page_range+0x76/0x150 migrate_vma_setup+0x18a/0x640 svm_migrate_vram_to_ram+0x245/0xa10 [amdgpu] svm_migrate_to_ram+0x36f/0x470 [amdgpu] do_swap_page+0xcfe/0xec0 __handle_mm_fault+0x96b/0x15e0 handle_mm_fault+0x13f/0x3e0 do_user_addr_fault+0x1e7/0x690 Fixes: e1f84eef ("drm/amdkfd: handle CPU fault on COW mapping") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
-
Yang Wang authored
align TMR BO size TO tmr size is not necessary, modify the size to 1M to avoid re-create BO fail when serious VRAM fragmentation. v2: add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
-
Candice Li authored
Enable full reset for RAS supported configuration on gc v11_0_0. v2: simplify the code. Signed-off-by:
-
Candice Li authored
Only check MCUMC_STATUS for CE counter for umc v8_10. Signed-off-by:
-
Charlene Liu authored
[why] update header files, and remove not used register access marco Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
-
Philip Yang authored
Prefaulting potentially allocates system memory pages before a migration. This adds unnecessary overhead. Instead we can skip unallocated pages in the migration and just point migrate->dst to a 0-initialized VRAM page directly. Then the VRAM page will be inserted to the PTE. A subsequent CPU page fault will migrate the page back to system memory. Signed-off-by:
-
Philip Yang authored
If CPU page fault in a page with zone_device_data svm_bo from another process, that means it is COW mapping in the child process and the range is migrated to VRAM by parent process. Migrate the parent process range back to system memory to recover the CPU page fault. Signed-off-by:
-
wangjianli authored
Delete the redundant word 'to'. Signed-off-by:
wangjianli <wangjianli@cdjrlc.com> Signed-off-by:
-
shaoyunl authored
For SRIOV configuration, host driver control the reset method(either FLR or heavier chain reset). The host will notify the guest individually with FLR message if individual GPU within the hive need to be reset. So for guest side, no need to use hive->reset_domain to replace the original per device reset_domain Signed-off-by:
-
Tom St Denis authored
The 10.3 GC headers were missing most of the pwrdec block. This patch adds the registers and bits present in the 10.1 header but based on the contents of the 10.3 specs. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
-
