- 08 Sep, 2016 6 commits
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Vladimir Barinov authored
This supports GPIO leds on H3ULCB board Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Vladimir Barinov authored
This supports SSI sound for H3ULCB board. SSI DMA mode used. CS2000 used as AUDIO_CLK_B. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Vladimir Barinov authored
This supports SDHI0 on H3ULCB board SD card slot Signed-off-by:
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Vladimir Barinov authored
This supports GPIO keys on H3ULCB board Signed-off-by:
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Simon Horman authored
Remove cap-mmc-highspeed property from SDHI2 and SDHI3. This property is unnecessary as the driver automatically sets the highspeed capability. Furthermore its use is inconsistent with SDHI0 and SDHI1 which are also highspeed capable but do not have this property present. Found by inspection. Signed-off-by: -
Vladimir Barinov authored
This supports USB2.0 Host channel 1 on H3ULCB board Signed-off-by:
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- 06 Sep, 2016 20 commits
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Vladimir Barinov authored
This supports USB2 PHY channel #1 on H3ULCB board Signed-off-by:
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Vladimir Barinov authored
This supports watchdog timer for H3ULCB board Signed-off-by:
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Vladimir Barinov authored
This enables EXTALR clock that can be used for the watchdog. Signed-off-by:
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Vladimir Barinov authored
This supports I2C2 bus on H3ULCB board Signed-off-by:
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Vladimir Barinov authored
This supports Ethernet AVB on H3ULCB board Signed-off-by:
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Vladimir Barinov authored
This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by:
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Vladimir Barinov authored
Add the initial device tree for the R8A7795 SoC based H3ULCB low cost board. This commit supports the following peripherals: - SCIF (console) Signed-off-by:
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Vladimir Barinov authored
Add H3ULCB Device tree bindings Documentation, listing it as a supported board. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Geert Uytterhoeven authored
The audio-dmac nodes used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by:
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Laurent Pinchart authored
Only the VGA output is supported for now. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
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Laurent Pinchart authored
Add the DU device to r8a7795.dtsi in a disabled state. Signed-off-by:
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Laurent Pinchart authored
The r8a7795 has 9 VSP instances. Signed-off-by:
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Laurent Pinchart authored
The FCPs handle the interface between various IP cores and memory. Add the instances related to the VSP2s. Signed-off-by:
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Yoshihiro Shimoda authored
Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Yoshihiro Shimoda authored
We have to set SW15 to pin 2-3 side on the board before we use CN9 as USB host or peripheral. Signed-off-by:
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Yoshihiro Shimoda authored
This patch also adds a regulator node for USB2.0 to handle VBUS on/off by the phy-rcar-gen3-usb2 driver. Signed-off-by:
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Yoshihiro Shimoda authored
Signed-off-by:
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Wolfram Sang authored
Define the upper limit otherwise the driver cannot utilize max speeds. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Kieran Bingham authored
Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Kieran Bingham <kieran@bingham.xyz> Signed-off-by:
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Kieran Bingham authored
Provide nodes for the FCP devices dedicated to the FDP device channels. Reviewed-by:
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- 19 Aug, 2016 3 commits
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Takeshi Kihara authored
This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
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Takeshi Kihara authored
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
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- 16 Aug, 2016 1 commit
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Laurent Pinchart authored
Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by:
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- 08 Aug, 2016 10 commits
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Sergei Shtylyov authored
Add DU pin groups to the R8A7792 PFC driver. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by:
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Geert Uytterhoeven authored
This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Sergei Shtylyov authored
Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by:
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Sergei Shtylyov authored
Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by:
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Sergei Shtylyov authored
Add the EtherAVB pin groups to the R8A7792 PFC driver. Signed-off-by:
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Sergei Shtylyov authored
Add the PFC support for the R8A7792 SoC including pin groups for some on-chip devices such as SCIF, INTC, and LBSC... Signed-off-by:
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Sergei Shtylyov authored
The PORT_GP_CFG_<n>() macros take up more than 80 columns -- and not for a good reason. Make the header file checkpatch.pl-proof at least in this respect... Signed-off-by:
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Ulrich Hecht authored
Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by:
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Linus Torvalds authored
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