- 31 Mar, 2015 32 commits
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James Hogan authored
Add support for early console of MIPS Fast Debug Channel (FDC) on channel 1 with a call very early from the MIPS setup_arch(). Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9145/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
Add TTY driver and consoles for the MIPS EJTAG Fast Debug Channel (FDC), which is found on the per-CPU MIPS Common Device Mapped Memory (CDMM) bus. The FDC is a per-CPU device which is used to communicate with an EJTAG probe. RX and TX FIFOs exist, containing 32-bits of data and 4-bit channel numbers. 16 general data streams are implemented on this for TTY and console use by encoding up to 4 bytes on each 32-bit FDC word. The TTY devices are named e.g. /dev/ttyFDC3c2 for channel 2 of the FDC attached to logical CPU 3. These can be used for getting the kernel log, a login prompt, or as a GDB remote transport, all over EJTAG and without needing a serial port. It can have an interrupt to notify of when incoming data is available in the RX FIFO or when the TX FIFO is no longer full. The detection of this interrupt occurs in architecture / platform code, but it may be shared with the timer and/or performance counter interrupt. Due to the per-CPU nature of the hardware, all outgoing TTY data is written out from a kthread which is pinned to the appropriate CPU. The console is not bound to a specific CPU, so output will appear on the chosen channel on whichever CPU the code is executing on. Enable with e.g. console=fdc1 in kernel arguments. /dev/console is bound to the same channel on the boot CPU's FDC if it exists. Signed-off-by:
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James Hogan authored
On certain cores (namely proAptiv and P5600) incoming data via a Fast Debug Channel (FDC) while the core is blocked on a wait instruction will cause the wait not to wake up even when another interrupt is received. This makes an idle target stop as soon as you send FDC data to it, until the debug probe interrupts it and restarts the wait instruction. This is worked around by avoiding using r4k_wait on these cores if CONFIG_MIPS_EJTAG_FDC_TTY is enabled (which would imply the user intends to use the FDC). [ralf@linux-mips.org: Fix conflict.] Signed-off-by:
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James Hogan authored
Implement the weak get_c0_fdc_int() function for Malta. The Fast Debug Channel (FDC) interrupt is obtained mainly depending on whether a GIC is present. Vectored external interrupt mode isn't yet supported. Signed-off-by:
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James Hogan authored
Add a function to the MIPS GIC driver for retrieving the Fast Debug Channel (FDC) interrupt number, similar to the existing ones for the timer and perf counter interrupts. This will be used by platform implementations of get_c0_fdc_int() if a GIC is present. A workaround exists for interAptiv and proAptiv which claim to be able to route the FDC interrupt but don't seem to be able to in practice (at least on Malta). [ralf@linux-mips.org: Fix conflict.] Signed-off-by:
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James Hogan authored
Treat the Fast Debug Channel (FDC) interrupt the same as the timer and performance counter interrupts. Like them, the FDC IRQ is also per-VPE, and also doesn't use a per-CPU device ID yet. Per-CPU device IDs don't seem to work with IRQF_SHARED which is needed for compatibility with cores which don't route the FDC IRQ through the GIC. For hardware which routes FDC IRQs through the GIC this is something that could be added later. Signed-off-by:
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James Hogan authored
Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC) interrupt from the IntCtl register and store it in cp0_fdc_irq where platform implementations of the new weak platform function get_c0_fdc_int() can refer to it. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by:
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James Hogan authored
Add architectural field definitions relating to the Fast Debug Channel (FDC) interrupt, namely the pending bit in Cause and the field in IntCtl to specify which CPU IRQ line the FDC interrupt is routed to. Signed-off-by:
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James Hogan authored
Implement mips_cdmm_phys_base() for Malta, returning the physical base address 0x1fc10000 which is "typically unused". This allows the Common Device Memory Map (CDMM) region to be mapped, and devices in that region (such as the Fast Debug Channel (FDC) hardware for communication over EJTAG) to be discovered. Signed-off-by:
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James Hogan authored
Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in the standard Linux device model. Each device attached via CDMM is discoverable via an 8-bit type identifier and may contain a number of blocks of memory mapped registers in the CDMM region. IRQs are expected to be handled separately. Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices, all the driver callbacks take place from workqueues which are run on the right CPU for the device in question, so that the driver doesn't need to be as concerned about which CPU it is running on. Callbacks also exist for when CPUs are taken offline, so that any per-CPU resources used by the driver can be disabled so they don't get forcefully migrated. CDMM devices are created as children of the CPU device they are attached to. Any existing CDMM configuration by the bootloader will be inherited, however platforms wishing to enable CDMM should implement the weak mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver knows where it should put the CDMM region in the physical address space if the bootloader hasn't already enabled it. A mips_cdmm_early_probe() function is also provided to allow early boot or particularly low level code to set up the CDMM region and probe for a specific device type, for example early console or KGDB IO drivers for the EJTAG Fast Debug Channel (FDC) CDMM device. Signed-off-by:
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James Hogan authored
Add architectural definitions and probing for the MIPS Common Device Memory Map (CDMM) region. When supported and enabled at a particular physical address, this region allows some number of per-CPU devices to be discovered and controlled via MMIO. A bit exists in Config3 to determine whether the feature is present, and a CDMMBase CP0 register allows the region to be enabled at a particular physical address. [ralf@linux-mips.org: Sort conflict with other patches.] Signed-off-by:
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James Hogan authored
Before release 2 of the architecture there weren't separate interrupt pending bits for the local CPU interrupts (timer & perf counter overflow), so when they were connected to the same interrupt line the timer handler had to call the performance counter handler before knowing whether a timer interrupt was actually pending. Now another CPU local interrupt, for the Fast Debug Channel (FDC), can also be routed to an arbitrary interrupt line. It isn't scalable to keep adding cross-calls between handlers for these cases of shared interrupt lines, especially since the FDC could in theory share its interrupt line with the performance counter, timer, or both. Fortunately since release 2 of the architecture separate interrupt pending bits do exist in the Cause register. This allows local interrupts which share an interrupt line to have separate handlers using IRQF_SHARED. Unfortunately they can't easily have their own irqchip as there is no generic way to individually mask them. Enable this sharing to happen by removing the special case for when the perf count shares an IRQ with the timer. cp0_perfcount_irq and cp0_compare_irq can then be set to the same value with shared interrupt handlers registered for both of them. Pre-R2 code should be unaffected. cp0_perfcount_irq will always be -1 and the timer handler will contnue to call into the perf counter handler. Signed-off-by:
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James Hogan authored
When requesting the performance counter overflow interrupt, pass flags which are compatible with the cevt-r4k driver, in particular IRQF_SHARED so that the two handlers can share the same IRQ. This is possible since release 2 of the architecture where there are separate pending interrupt bits for the timer interrupt and the performance counter interrupt. This will be necessary since the FDC interrupt can also be arbitrarily routed to a CPU interrupt, possibly sharing with the timer, the performance counters, or both, and it isn't scalable to have all the handlers able to call other handlers that may be on the same IRQ line. Signed-off-by:
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James Hogan authored
When requesting the performance counter overflow interrupt, pass flags which are compatible with the cevt-r4k driver, in particular IRQF_SHARED so that the two handlers can share the same IRQ. This is possible since release 2 of the architecture where there are separate pending interrupt bits for the timer interrupt and the performance counter interrupt. This will be necessary since the FDC interrupt can also be arbitrarily routed to a CPU interrupt, possibly sharing with the timer, the performance counters, or both, and it isn't scalable to have all the handlers able to call other handlers that may be on the same IRQ line. Shared handlers must also have a unique device pointer so they can be individually removed, so &mipspmu is now passed in for that instead of NULL. Signed-off-by:
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Ralf Baechle authored
The attempt to get gcc to generate best possible code turned c0_compare_interrupt() into a bit of Italian pasta code. Tweak for sanity. Signed-off-by: -
James Hogan authored
Make the cevt-r4k interrupt handler shared so that other interrupt handlers (specifically the performance counter overflow handler and fast debug channel interrupt handler) can share the same interrupt line. This simply imvolves returning IRQ_NONE when no timer interrupt has been handled to allow other handlers to run, and passing IRQF_SHARED when setting up the IRQ handler so that other handlers (with compatible flags) can be registered. Signed-off-by:
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James Hogan authored
Add missing VPE_PEND, VPE_RMASK and VPE_SMASK definitions for the local FDC interrupt. These local interrupt definitions aren't directly used, but if they exist they should be complete. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9127/Signed-off-by:
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James Hogan authored
Fix typo in comment in gic_get_c0_perfcount_int: "erformance" -> "performance". Signed-off-by:
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James Hogan authored
The situation where the timer interrupt is on the same line as the performance counter interrupt is handled in per_cpu_trap_init() by setting cp0_perfcount_irq to -1, so there is no need to duplicate the logic conditional upon cp0_perfcount_irq >= 0 in perf (init_hw_perf_events()) and oprofile (mipsxx_init()). Signed-off-by:
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James Hogan authored
Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than the magic values (1 << 30) and (1 << 26). Signed-off-by:
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James Hogan authored
Long ago, commit 8531a35e ("[MIPS] SMTC: Fix SMTC dyntick support.") moved handle_perf_irq() out of cevt-r4k.c into a header so it could be shared with cevt-smtc.c. Slightly less long ago, commit b633648c ("MIPS: MT: Remove SMTC support") removed all traces of SMTC support, including cevt-smtc.c, leaving cevt-r4k.c once again the sole user of handle_perf_irq(), therefore move it back into cevt-r4k.c from the header. Signed-off-by:
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Govindraj Raja authored
Add a defconfig for Pistachio which enables drivers for all the currently supported peripherals on the SoC. Signed-off-by:
Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by:
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Andrew Bresticker authored
Add initial support for boards based on the Imagination Pistachio SoC. Pistachio is based on a dual-core MIPS interAptiv CPU and will boot using device-tree. Signed-off-by:
James Hartley <james.hartley@imgtec.com> Signed-off-by:
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Andrew Bresticker authored
The Pistachio SoC boots only with device-tree. Document the required properties and nodes as well as the boot protocol between the bootlaoder and the kernel. Signed-off-by:
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Andrew Bresticker authored
Platforms which use raw zboot images may need to link the image at a fixed address if there is no other way to communicate the load address to the bootloader. Allow the per-platform Kbuild files to specify an optional zboot image load address (zload-y) and fall back to calc_vmlinuz_load_addr if unset. Signed-off-by:
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Kevin Cernekee authored
11 platforms require at least one of these workarounds to be enabled; 22 platforms do not. In the latter case we can fall back to a generic version. Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR. Suggested-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Signed-off-by:
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Andrew Bresticker authored
Register the clock gates for the external audio and ethernet reference clocks provided by the top-level general control block. Signed-off-by:
Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Patchwork: https://patchwork.linux-mips.org/patch/9321/Signed-off-by:
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Andrew Bresticker authored
Register the system interface gate clocks provided by the peripheral general control block. These clocks gate register access for various peripherals. Signed-off-by:
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Andrew Bresticker authored
Register the clocks generated by the peripheral clock controller. This includes the clocks for several peripherals, including I2C, PWM, watchdog, and timer. Signed-off-by:
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Andrew Bresticker authored
Register the clocks generated by the core clock controller. This includes the 7 PLLs and clocks for the CPU, RPU co-processor, audio, WiFi, bluetooth, and several other peripherals. The MIPS and PERIPH_SYS clocks must remain enabled at all times. Signed-off-by:
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Andrew Bresticker authored
Add a driver for the integer (GF40LP_LAINT) and fractional (GF40LP_FRAC) PLLs present on Pistachio. Signed-off-by:
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Andrew Bresticker authored
Add helpers for registering clocks and clock providers on Pistachio. Signed-off-by:
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- 27 Mar, 2015 1 commit
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Andrew Bresticker authored
Add a device-tree binding document describing the four clock controllers present on the IMG Pistachio SoC. Signed-off-by:
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- 24 Mar, 2015 7 commits
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Aaro Koskinen authored
Enable user to select OCTEON SHA1/256/512 modules. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: David S. Miller <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9492/Signed-off-by:
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Aaro Koskinen authored
Add OCTEON SHA512 module. Signed-off-by:
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Aaro Koskinen authored
Add OCTEON SHA256 module. Signed-off-by:
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Aaro Koskinen authored
Add OCTEON SHA1 module. Signed-off-by:
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Aaro Koskinen authored
Add instruction definitions for SHA1/256/512. Signed-off-by:
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Aaro Koskinen authored
Always disable preemption on behalf of the drivers when crypto engine is taken into use. This will simplify the usage. Signed-off-by:
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Aaro Koskinen authored
Don't disable bottom half while the crypto engine is in use, as it should be unnecessary: All kernel crypto engine usage is wrapped with crypto engine state save/restore, so if we get interrupted by softirq that uses crypto they should save and restore our context. This actually fixes an issue when running OCTEON MD5 with interrupts disabled (tcrypt mode=302). There's a WARNING because the module is trying to enable the bottom half with irqs disabled: [ 52.656610] ------------[ cut here ]------------ [ 52.661439] WARNING: CPU: 1 PID: 428 at /home/aaro/git/linux/kernel/softirq.c:150 __local_bh_enable_ip+0x9c/0xd8() [ 52.671780] Modules linked in: tcrypt(+) [...] [ 52.763539] [<ffffffff8114082c>] warn_slowpath_common+0x94/0xd8 [ 52.769465] [<ffffffff81144614>] __local_bh_enable_ip+0x9c/0xd8 [ 52.775390] [<ffffffff81119574>] octeon_md5_final+0x12c/0x1e8 [ 52.781144] [<ffffffff81337050>] shash_compat_digest+0xd0/0x1b0 Signed-off-by:
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