- 25 Feb, 2019 40 commits
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Gustavo A. R. Silva authored
In preparation to enabling -Wimplicit-fallthrough, mark switch cases according to what the compiler looks for, where we are expecting to fall through. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Thomas Petazzoni authored
The SDHCI core is know properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-tegra code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@bootlin.com> Tested-by:
Thierry Reding <treding@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
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Thomas Petazzoni authored
The SDHCI core is now properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-omap code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by:
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Thomas Petazzoni authored
Even though SDHCI controllers may have a dedicated WP pin that can be queried using the SDHCI_PRESENT_STATE register, some platforms may chose to use a separate regular GPIO to route the WP signal. Such a GPIO is typically represented using the wp-gpios property in the Device Tree. Unfortunately, the current sdhci_check_ro() function does not make use of such GPIO when available: it either uses a host controller specific ->get_ro() operation, or uses the SDHCI_PRESENT_STATE. Several host controller specific ->get_ro() functions are implemented just to check a WP GPIO state. Instead of pushing this to more controller-specific implementations, let's handle this in the core SDHCI code, just like it is already done for the CD GPIO in sdhci_get_cd(). The below patch simply changes sdhci_check_ro() to use the value of the WP GPIO if available. Signed-off-by:
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Linus Walleij authored
The WMT SDMMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> so drop this surplus include. Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
The Sunxi MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Andre Przywara <andre.przywara@arm.com> Cc: cenowy Zheng <icenowy@aosc.io> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
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Linus Walleij authored
The SDHCI PXAv2 driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> so drop this surplus include. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
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Linus Walleij authored
The SDHCI BCM Kona driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
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Linus Walleij authored
The MXS-MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
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Linus Walleij authored
The MXCMMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Jun Qian <hangdianqj@163.com> Cc: Matteo Facchinetti <matteo.facchinetti@sirius-es.it> Signed-off-by:
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Colin Ian King authored
There is an if block that is not indented, fix this. Also add a break statement on the default case to clean up a cppcheck warning. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Avri Altman authored
SD specs version 4.x and 5.x have a dedicated slices in the SCR register. Higher versions will rely on a combination of the existing fields. Signed-off-by:
Avri Altman <avri.altman@wdc.com> Signed-off-by:
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Avri Altman authored
In MMC, the discard arg is a read-only ext_csd parameter - set it once on card init. To be consistent, do that for SD as well even though its discard arg is always 0x0. Signed-off-by:
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Linus Walleij authored
The argument "override_active_level" made it possible to enforce a specific polarity on the write-protect GPIO line. All callers in the kernel pass "false" to this call after I have converted all drivers to use GPIO machine descriptors, so remove the argument and clean out this. This kind of polarity inversion should be handled by the GPIO descriptor inside the GPIO library if needed. This rids us of one instance of the kludgy calls into the gpiod_get_raw_value() API. Signed-off-by:
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Lukas Wunner authored
The BCM2835 MMC host driver sets the device's driver data pointer to NULL on ->remove() even though the driver core subsequently does the same in __device_release_driver(). Drop the duplicate assignment. Tested-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Signed-off-by:
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Lukas Wunner authored
The BCM2835 MMC host driver uses a pointer to get from the private bcm2835_host structure to the generic mmc_host structure. However the latter is always immediately preceding the former in memory, so compute its address with a subtraction (which is cheaper than a dereference) and drop the superfluous pointer. No functional change intended. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Lukas Wunner authored
bcm2835_add_host() invokes IS_ERR_OR_NULL() on a DMA channel pointer, however dma_request_slave_channel() (which was used to populate the pointer) never returns an error pointer. So a NULL pointer check is sufficient. Tested-by:
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Aaro Koskinen authored
When running OMAP1 kernel on QEMU, MMC access is annoyingly noisy: MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! [ad inf.] Emulator warnings appear to be valid. The TI document SPRU680 [1] ("OMAP5910 Dual-Core Processor MultiMedia Card/Secure Data Memory Card (MMC/SD) Reference Guide") page 36 states that the maximum timeout is 253 cycles and "0xff and 0xfe cannot be used". Fix by using 0xfd as the maximum timeout. Tested using QEMU 2.5 (Siemens SX1 machine, OMAP310), and also checked on real hardware using Palm TE (OMAP310), Nokia 770 (OMAP1710) and Nokia N810 (OMAP2420) that MMC works as before. [1] http://www.ti.com/lit/ug/spru680/spru680.pdf Fixes: 730c9b7e ("[MMC] Add OMAP MMC host driver") Signed-off-by:Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
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Sowjanya Komatineni authored
This patch adds HW Command Queue for supported Tegra SDMMC controllers. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
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Sowjanya Komatineni authored
Below are the supported DMA types in Host Control1 Register with Version 4 enable b'00 - SDMA b'01 - Not Used b'10 - ADMA2 b'11 - ADMA2 or ADMA3 ADMA3 uses Command Descriptor to issue an SD command. A multi-block data transfer is performed by using a pair of CMD descriptor and ADMA2 descriptor. ADMA3 performs multiple of multi-block data transfer by using Integrated Descriptor which is more suitable for Command Queuing to fetch both Command and Transfer descriptors. Host Capabilities register indicates the supports of ADMA3 DMA. Signed-off-by:
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Sowjanya Komatineni authored
Add supports-cqe optional property for MMC hosts. This property is used to identify the specific host controller supporting command queue. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Ulf Hansson authored
The git tree isn't used to maintain SDHCI, but instead we use the common MMC git tree. Let's drop it to avoid confusion. Signed-off-by:
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Ulf Hansson authored
The eMMC CQHCI is the host controller interface, introduced in the eMMC spec v5.1. The code was originally developed as collaboration among several people, however none really stepped in to maintain it. Let's add Adrian Hunter (Intel), Ritesh Harjani and Asutosh Das as the maintainers, whom knows both the code and the spec. Cc: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by:
Ritesh Harjani <riteshh@codeaurora.org> Acked-by:
Asutosh Das <asutoshd@codeaurora.org>
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Nicolas Ferre authored
This patch adds support for 8-bit buswidth. Relevant SDCR value modified. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Takeshi Saito authored
This fixes card initialization failure in high speed mode. If U-Boot uses SDR or HS200/400 mode before starting Linux and Linux DT does not enable SDR/HS200/HS400 mode, card initialization fails in high speed mode. It is necessary to initialize SCC registers during card initialization phase. HW reset function is registered only for a port with either of SDR/HS200/HS400 properties in device tree. If SDR/HS200/HS400 properties are not present in device tree, SCC registers will not be reset. In SoC that support SCC registers, HW reset function should be registered regardless of the configuration of device tree. Reproduction procedure: - Use U-Boot that support MMC HS200/400 mode. - Delete HS200/HS400 properties in device tree. (Delete mmc-hs200-1_8v and mmc-hs400-1_8v) - MMC port works high speed mode and all commands fail. Signed-off-by:
Takeshi Saito <takeshi.saito.xv@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Cc: Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Cc: stable@vger.kernel.org Signed-off-by:
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Paul Cercueil authored
Drop the custom code to get the 'cd' and 'wp' GPIOs. The driver now calls mmc_of_parse() which will init these from devicetree or device properties. Also drop the custom code to get the 'power' GPIO. The MMC core provides us with the means to power the MMC card through an external regulator. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Reviewed-by:
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Ernest Zhang(WH) authored
O2 SD host controller only need set the quirk2 flag SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD when work on force 1.8v emmc mode but not normal mode Signed-off-by:
Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by:
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Mathieu Malaterre authored
There is a plan to build the kernel with -Wimplicit-fallthrough and these places in the code produced warnings (W=1). This commit removes the following warnings: drivers/mmc/host/jz4740_mmc.c:745:3: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/mmc/host/jz4740_mmc.c:779:3: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
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Wei Yongjun authored
In case of error, the function devm_kzalloc() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: fadac7488064 ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by:Wei Yongjun <weiyongjun1@huawei.com> Acked-by:
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Mathieu Malaterre authored
There is a plan to build the kernel with -Wimplicit-fallthrough and this place in the code produced a warning (W=1). In this particular case rewrote the comment to start with the string "fall through", so as to match the regular expression expected by GCC. Truncate the comment slightly to fit the max line length of 80 characters. This commit remove the following warning: drivers/mmc/core/host.c:196:14: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by:
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Sowjanya Komatineni authored
Program initial drive code offsets which will be used by auto calibration process. Program fixed drive strengths for SDMMC pads in pad control register when auto cal timeouts. Fixed settings are based on Pre-SI analysis of the pad design. Signed-off-by:
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Sowjanya Komatineni authored
Add pinctrls for 3V3 and 1V8 pad drive strength configuration for Tegra210 sdmmc. Tegra210 sdmmc has pad configuration registers in pinmux register domain and handled thru pinctrl to pinmux device node. Tegra186 and Tegra194 has pad configuration register with in the SDMMC register domain itself and are handles thru drive strength properties in sdmmc device node. Signed-off-by:
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BOUGH CHEN authored
Currently, USDHC do not generate transfer complete interrupt when send a non-data-command with R1b response. But if want to support DCMD in CMDQ, need to change this, the DCMD IC logic require the USDHC to enable this function, otherwise DCMD will never get a CC(command complete) interrupt. This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
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BOUGH CHEN authored
Add CMDQ support for imx8qm/imx8qxp. Signed-off-by:
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BOUGH CHEN authored
Change to use sdhci_set_timeout() to set the maximum timeout, so that the host can use it's own set_timeout() callback to set the maximum timeout if the host has. Signed-off-by:
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BOUGH CHEN authored
Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode support. Signed-off-by:
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BOUGH CHEN authored
For some eMMC, after switch to HS400ES mode, it need to config the strobe dll target dealy even if the clock is 50MHZ or 25MHz, otherwise will meet CMD index/crc error when send CMD13 to check the switch status. [ 2.473915] IRQ status 0x000a8001 [ 2.473934] mmc2: mmc_select_hs400es failed, error -84 [ 2.473938] mmc2: error -84 whilst initialising MMC card Signed-off-by:
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Niklas Söderlund authored
When removing the driver make sure to undo the PM autosuspend configured when probing the host. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
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Niklas Söderlund authored
Signed-off-by:
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wangbo authored
In sdio_bus_remove the variable is unneeded,remove it now. Signed-off-by:
wangbo <wang.bo116@zte.com.cn> Signed-off-by:
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