- 20 Oct, 2015 5 commits
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Michael Turquette authored
Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.4-rc1 This contains a patch that allows the DFLL to use clock rates higher than 2^31-1 Hz by using the ->determine_rate() operation instead of the ->round_rate() operation. Other than that there's a couple of cleanups in preparation for Tegra210 support.
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Rhyland Klein authored
tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by:
Benson Leung <bleung@chromium.org> Signed-off-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by:
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Rhyland Klein authored
Some fields moved from the tegra_clk_pll struct to the tegra_pll_params struct. Update the struct comments to reflect where the fields really are. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by:
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Thierry Reding authored
The monitor code is used with DEBUG_FS only, so move it into the corresponding #ifdef block to avoid potential compiler warnings. Signed-off-by:
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- 19 Oct, 2015 1 commit
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Geliang Tang authored
s/regsiter/register/ Signed-off-by:
Geliang Tang <geliangtang@163.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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- 16 Oct, 2015 10 commits
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Stephen Boyd authored
This reverts commit e79b202c. Now that we use of_clk_get() inside of_clk_get_parent_name() we can safely use it here. Signed-off-by:
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Archit Taneja authored
Add rcg and branch clk structs for DSI1 and DSI2 blocks found in MSM8960 and APQ8064. Each DSI instance has 4 pairs of rcg and branch clocks. Populate arrays mmcc_msm8960_clks and mmcc_apq8064_clks with these clocks. Signed-off-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
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Archit Taneja authored
DSI specific RCG clocks required customized clk_ops. There are a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL. There are a total of 2 clocks coming from the DSI PLL, which serve as inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by another divider of the PLL. In each of the 2 groups above, only one of the clocks sets its parent. These are BYTE RCG and DSI RCG for each of the groups respectively, as shown in the diagram below. The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't take in a freq table, since the DSI driver using these clocks is parent-able. The PIXEL RCG needs to derive the required pixel clock using dsixpll. It parses a m/n frac table to retrieve the correct clock. The ESC RCG doesn't have a frac M/N block, it can just apply a pre- divider. Its ops simply check if the required clock rate can be achieved by the pre-divider. +-------------------+ | |---dsixpllbyte---o---> To byte RCG | | | (sets parent rate) | | | | | | | DSI 1/2 PLL | | | | o---> To esc RCG | | (doesn't set parent rate) | | | |----dsixpll-----o---> To dsi RCG +-------------------+ | (sets parent rate) ( x = 1, 2 ) | | o---> To pixel rcg (doesn't set parent rate) Signed-off-by: -
Stephen Boyd authored
This include doesn't look to be used, and compiling this file on arm64 still works, so remove it. Signed-off-by: -
Javier Martinez Canillas authored
These drivers only have runtime but no build time dependencies so can be built for testing purposes if the Kconfig COMPILE_TEST option is enabled. This is useful to have more build coverage and make sure that drivers are not affected by changes that could cause build regressions. Signed-off-by:
Javier Martinez Canillas <javier@osg.samsung.com> Acked-by:
Scott Branden <sbranden@broadcom.com> Signed-off-by:
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Geert Uytterhoeven authored
When calling __clk_get_name() on a const clock: warning: passing argument 1 of '__clk_get_name' discards 'const' qualifier from pointer target type include/linux/clk-provider.h:613:13: note: expected 'struct clk *' but argument is of type 'const struct clk *' __clk_get_name() does not modify the passed clock, hence make it const. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
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Geert Uytterhoeven authored
r8a7778_rates[] and r8a7778_divs[] are only used in clk-r8a7778.c, and never modified. Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
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Stephen Boyd authored
Merge tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX updates from Shawn Guo: "The i.MX clock updates for 4.4: - A couple of fixes on i.MX31 and i.MX35 clock initialization functions which makes mxc_timer_init() currently be called twice for DT boot. - Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal design target. - Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for Vybrid, and SPDIF_GCLK for i.MX6. - A series from Lucas to fix early debug UART clock setup. This is currently a one-off fix for i.MX platform, and can be extended to become a generic solution later." * tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx6: Add SPDIF_GCLK clock in clock tree clk: imx7d: add ADC root clock clk: imx31: Do not call mxc_timer_init twice when booting with DT clk: imx7d: retain early UART clocks during kernel init clk: imx6: retain early UART clocks during kernel init clk: imx5: retain early UART clocks during kernel init clk: imx35: retain early UART clocks during kernel init clk: imx31: retain early UART clocks during kernel init clk: imx27: retain early UART clocks during kernel init clk: imx25: retain early UART clocks during kernel init clk: imx: add common logic to detect early UART usage clk: imx35: Do not call mxc_timer_init twice when booting with DT clk: clk-vf610: Add clock for Vybrid OCOTP controller clk: imx: increase AXI clock rate to 264MHz for i.MX6UL
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- 15 Oct, 2015 2 commits
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Stephen Boyd authored
If a clock provider has #clock-cells = 1 and we call of_clk_get_parent_name() on it we may end up returning the name of the provider node if the provider doesn't have a clock-output-names property. This doesn't make sense, especially when you consider that calling of_clk_get_parent_name() on such a node with different indices will return the same name each time. Let's try getting the clock from the framework via of_clk_get() instead, and only fallback to the node name if we have a provider with #clock-cells = 0. This way, we can't hand out the same name for different clocks when we don't actually know their names. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: -
Stephen Boyd authored
* clk-fixes: Partially revert "clk: mvebu: Convert to clk_hw based provider APIs"
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- 14 Oct, 2015 2 commits
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Javier Martinez Canillas authored
The email address listed in MODULE_AUTHOR() no longer exist so to prevent people to send emails to the old address, replace it with my current one. Signed-off-by:
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Stephen Boyd authored
This partially reverts commit eca61c9f. Thomas reports that it causes regressions on Armada XP devices. This is because of_clk_get_parent_name() relies on the property 'clock-output-names' to resolve the name of a clock's parent, without trying to get the clock from the framework and call __clk_get_name(). Given that Armada XP devices don't have the 'clock-output-names' property, of_clk_get_parent_name() returns the name of the node which doesn't match the actual parent clock's name at all, causing CPU clocks to never link up with their parents. Reported-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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- 12 Oct, 2015 4 commits
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Julia Lawall authored
for_each_child_of_node performs an of_node_put on each iteration, so putting an of_node_put before a continue results in a double put. The semantic match that finds this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; iterator name for_each_child_of_node; @@ for_each_child_of_node(root, child) { ... when != of_node_get(child) * of_node_put(child); ... * continue; } // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Stephen Boyd authored
* clk-bcm2835: clk: bcm2835: Add support for programming the audio domain clocks clk: bcm2835: Add binding docs for the new platform clock driver. clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.
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Eric Anholt authored
This adds support for enabling, disabling, and setting the rate of the audio domain clocks. It will be necessary for setting the pixel clock for HDMI in the VC4 driver and let us write a cpufreq driver. It will also improve compatibility with user changes to the firmware's config.txt, since our previous fixed clocks are unaware of it. The firmware also has support for configuring the clocks through the mailbox channel, but the pixel clock setup by the firmware doesn't work, and it's Raspberry Pi specific anyway. The only conflicts we should have with the firmware would be if we made firmware calls that result in clock management (like opening firmware V3D or ISP access, which we don't support in upstream), or on hardware over-thermal or under-voltage (when the firmware would rewrite PLLB to take the ARM out of overclock). If that happens, our cached .recalc_rate() results would be incorrect, but that's no worse than our current state where we used fixed clocks. The existing fixed clocks in the code are left in place to provide backwards compatibility with old device tree files. Signed-off-by:
Eric Anholt <eric@anholt.net> Tested-by:
Martin Sperl <kernel@martin.sperl.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
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Shengjiu Wang authored
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by:
Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- 09 Oct, 2015 11 commits
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Rajendra Nayak authored
8960 family of devices have TSENS as part of GCC in hardware. Hence DT would represent a GCC node with GCC properties as well as TSENS. Create a virtual platform child device here for TSENS so the driver can probe it and use the parent (GCC) to extract DT properties. Suggested-by:
Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Massaged to work with devm friendly qcom_cc_probe()] Signed-off-by:
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Stephen Boyd authored
Having this hidden config below the COMMON_CLK_QCOM config causes menuconfig to stop indenting config items after it. <*> Support for Qualcomm's clock controllers {M} APQ8084 Global Clock Controller <M> APQ8084 Multimedia Clock Controller {M} IPQ806x Global Clock Controller <M> IPQ806x LPASS Clock Controller <M> MSM8660 Global Clock Controller <M> MSM8916 Global Clock Controller {M} APQ8064/MSM8960 Global Clock Controller <M> APQ8064/MSM8960 LPASS Clock Controller <M> MSM8960 Multimedia Clock Controller {M} MSM8974 Global Clock Controller <M> MSM8974 Multimedia Clock Controller Move it up above anything else so that we don't get odd indenting. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: -
Stephen Boyd authored
Now that qcom_cc_remove() is a nop, drop calls to qcom_cc_remove() and any empty driver remove functions. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: -
Stephen Boyd authored
Some APIs in qcom_cc_probe() don't have a devm counterpart, so we have to use the calling device's platform data to pass pointers to the remove path. Let's use devm_add_action() instead, so that the remove path doesn't need to do anything, allowing us to remove qcom_cc_remove() entirely. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: -
Gabriel Fernandez authored
Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by:
Pankaj Dev <pankaj.dev@st.com> Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by:
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Gabriel Fernandez authored
Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by:
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Gabriel Fernandez authored
The patch adds support for enable/disable of the Clockgen PLLs. clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs. Signed-off-by:
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Stephen Boyd authored
The oxili_cx GDSC is inside the power domain of the oxili GDSC. Add the dependency so that the CX domain can properly power up. Reported-by:
Rob Clark <robdclark@gmail.com> Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
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Stephen Boyd authored
Export these symbols so they can be used in loadable kernel modules. Cc: Rob Clark <robdclark@gmail.com> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Kevin Hilman <khilman@kernel.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Rafael J. Wysocki <rjw@rjwysocki.net> Signed-off-by:
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Mike Looijmans authored
This patch adds the driver and devicetree documentation for the Silicon Labs SI514 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 100kHz to 250MHz. Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Drop clk.h include, remove some casts] Signed-off-by:
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Haibo Chen authored
Add ADC root clock support in imx7d clock tree. Signed-off-by:
Haibo Chen <haibo.chen@freescale.com> Acked-by:
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- 02 Oct, 2015 5 commits
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https://github.com/jamesjjliao/linuxStephen Boyd authored
Pull mediatek clock support and fixes from James Liao: "This is a collection of new Mediatek clocks support and fixes. These patches come from Joe and me, including clock support for subsystems, GPT and some minor fixes." * 'v4.3-rc3-clk' of https://github.com/jamesjjliao/linux: clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS clk: mediatek: Add subsystem clocks of MT8173 dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers clk: mediatek: Fix rate and dependency of MT8173 clocks clk: mediatek: Add fixed clocks support for Mediatek SoC. clk: mediatek: Add __initdata and __init for data and functions clk: mediatek: Remove unused code from MT8173. clk: mediatek: Removed unused dpi_ck clock from MT8173 clk: mediatek: add 13mhz clock for MT8173
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Stephen Boyd authored
drivers/clk/samsung/clk-exynos7.c:896:33: warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should it be static? drivers/clk/samsung/clk-exynos7.c:1010:33: warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should it be static? Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: -
git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull updates from Sylwester Nawrocki: "Fixes, improvements and addition of some missing features of the exynos7 clock controller driver." * tag 'clk-samsung-4.4' of git://linuxtv.org/snawrocki/samsung: clk: samsung: exynos7: Add required clock tree for UFS clk: samsung: exynos7: Add missing fixed_clks to cmu_info clk: samsung: exynos7: Correct CMU_FSYS1 clocks names clk: samsung: exynos7: Correct CMU_FSYS0 clocks names clk: samsung: exynos7: Correct CMU_PERIS clocks names clk: samsung: exynos7: Correct CMU_PERIC1 clocks names clk: samsung: exynos7: Correct CMU_PERIC0 clocks names clk: samsung: exynos7: Correct CMU_CCORE clocks names clk: samsung: exynos7: Correct CMU_TOP1 clocks names clk: samsung: exynos7: Correct CMU_TOP0 clocks names clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC clk: samsung: exynos7: Change the CMU_TOPC block clock names clk: samsung: exynos7: Correct nr_clk_ids for fsys1 clk: samsung: exynos7: Correct nr_clk_ids for fsys0 clk: samsung: exynos7: Fix CMU TOP1 block clk: samsung: exynos7: Fix CMU TOPC block clock
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Stephen Boyd authored
* clk-fixes: (3 commits) clk: ti: dflt: fix enable_reg validity check clk: ti: fix dual-registration of uart4_ick clk: ti: clk-7xx: Remove hardwired ABE clock configuration
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Andy Shevchenko authored
We have couple of standard but rare used baudrates which are not supported by 1,8432MHz reference frequency. Besides that user can potentially ask for any baudrate (via BOTHER flag) and we currently don't fully support that. Since clk-fractional-divider is moved to use rational best approximation for reference frequency we may amend the driver to support whatever user wants. Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
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