- 07 Jul, 2022 8 commits
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Nícolas F. R. A. Prado authored
Add support for the ChromeOS Embedded Controller present on the Asurada platform. It is connected through the SPI1 bus and offers several functionalities: base detection, PWM controller, I2C tunneling, regulators, Type-C connector management, keyboard and Smart Battery Metrics (SBS). Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220629155956.1138955-8-nfraprado@collabora.comSigned-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Nícolas F. R. A. Prado authored
The Asurada platform has five I2C controllers and two SPI controllers that are used. In preparation for enabling the devices connected to these controllers, enable and configure their busses. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add system-wide power supplies present on all of the boards in the Asurada family. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220629155956.1138955-6-nfraprado@collabora.comSigned-off-by:
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Nícolas F. R. A. Prado authored
Add the gpio-line-names property to gpio-controller in order to document the usage of GPIOs on the Asurada platform. Signed-off-by:
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Nícolas F. R. A. Prado authored
Introduce the MT8192 Asurada Chromebook platform, including the Asurada Spherion and Asurada Hayato boards. This is enough configuration to get serial output working on Spherion and Hayato. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add binding for the Google Hayato board. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220629155956.1138955-3-nfraprado@collabora.comSigned-off-by:
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Nícolas F. R. A. Prado authored
Add binding for the Google Spherion board, which is used for Acer Chromebook 514 (CB514-2H). Signed-off-by:
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AngeloGioacchino Del Regno authored
Add a phandle to the MT8183_POWER_DOMAIN_MFG_ASYNC power domain and assign the GPU VSRAM supply to this in mt8183-kukui: this allows to keep the sram powered up while the GPU is used. Signed-off-by:
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- 22 Jun, 2022 22 commits
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Allen-KH Cheng authored
This commit adds dt-binding documentation for the MediaTek MT8186 reference board. Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by:
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Allen-KH Cheng authored
Add mt8186 pericfg compatible to binding document. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the maintenance interrupt for GIC-400. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add a node for the pinctrl controller found on MT6795 but without configuration for any pin, as that's expected to be done in the machine-specific devicetrees. Signed-off-by:
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AngeloGioacchino Del Regno authored
This SoC features an ARM CCI-400 IP: add the required node and assign the cci control ports to the CPU cores. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the timer node, enabling two GPTs, of which one will be used as sched_clock. Signed-off-by:
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AngeloGioacchino Del Regno authored
Remove the RTC and UART fixed clocks, as these were introduced to temporarily provide a dummy clock to devices: since the two 26M/32K fixed oscillators clocks (which do really exist in the SoC) have been added, there's no reason to keep the aforementioned (and now redundant) dummies in this devicetree. In order to remove the uart dummy clock, it was necessary to also reassign the clock of all UART nodes to clk26m. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features two always on oscillators running at the aforementioned frequencies. Signed-off-by:
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AngeloGioacchino Del Regno authored
At least on commercial devices like some smartphones, the bootloader will initialize the SoC watchdog and set it to reboot the board when it times out. The last pet that this watchdog is getting is right before booting the kernel and left it enabled as a protection against boot failure: this means that Linux is expected to initialize this device and pet as soon as possible, or it will bark and reset the AP. In order to prevent that, add the required watchdog node as default enabled: this will have no side effects on boards that are not performing the aforementioned watchdog setup before booting Linux. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the required nodes to enable the PMU on this SoC. Signed-off-by:
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AngeloGioacchino Del Regno authored
This SoC is HMP and has two clusters with four Cortex-A53 cores each: declare a cpu map and, while at it, also add the next-level-cache properties. Signed-off-by:
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AngeloGioacchino Del Regno authored
MMIO devices should be inside of a soc bus node, as it's done for the vast majority of ARM64 devicetrees, and for almost all MTK devicetrees. Create a simple-bus soc node and move all devices with a MMIO address space in there. Signed-off-by:
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Krzysztof Kozlowski authored
gpio-keys (regular, not polling) does not use "poll-interval" property. Signed-off-by:
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AngeloGioacchino Del Regno authored
The IOMMU driver now looks for the "mediatek,infracfg" phandle as a new way to retrieve a syscon to that: even though the old way is retained, it has been deprecated and the driver will write a message in kmsg advertising to use the phandle way instead. For this reason, assign the right phandle to mediatek,infracfg in the iommu node. Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220616110830.26037-5-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
The IOMMU driver now looks for the "mediatek,infracfg" phandle as a new way to retrieve a syscon to that: even though the old way is retained, it has been deprecated and the driver will write a message in kmsg advertising to use the phandle way instead. For this reason, assign the right phandle to mediatek,infracfg in the iommu node. Signed-off-by:
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Chunfeng Yun authored
Use the fixed "efuse" name for efuse nodes according to its yaml file Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220617093132.22578-4-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Need also provide a specific compatible "mediatek,mt8192-efuse" at the same time when use the generic compatible "mediatek,efuse". Signed-off-by:
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Nícolas F. R. A. Prado authored
The entry-method property of the idle-states node should be "psci" as described in the idle-states binding, since this is already the value of enable-method in the CPU nodes. Fix it to get rid of a dtbs_check warning. Fixes: 9260918d ("arm64: dts: mt8192: Add cpu-idle-states") Signed-off-by:
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Nícolas F. R. A. Prado authored
Tweak the name of the idle-states subnodes so that they follow the binding pattern, getting rid of dtbs_check warnings. Only the usage of "-" in the name was necessary, but "off" was also exchanged for "sleep" since that seems to be a more common wording in other dts files. Fixes: 9260918d ("arm64: dts: mt8192: Add cpu-idle-states") Signed-off-by:
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Fabio Estevam authored
As explained in Documentation/devicetree/bindings/mmc/mmc-controller.yaml, the 'enable-sdio-wakeup' property is considered deprecated. Replace it with the 'wakeup-source' property instead. Signed-off-by:
Fabio Estevam <festevam@denx.de> Link: https://lore.kernel.org/r/20220621124435.121740-1-festevam@gmail.comSigned-off-by:
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Rex-BC Chen authored
We will use mediatek clock reset as infracfg_ao reset instead of ti-syscon. To support this, remove property of ti reset and add property of #reset-cells for mediatek clock reset. Signed-off-by:
Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by:
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Rex-BC Chen authored
To support reset of infra, we add property of #reset-cells. Signed-off-by:
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- 17 Jun, 2022 7 commits
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Moudy Ho authored
In order to allow modules with latency requirements such as MDP3 to set registers through CMDQ, add the relevant dts property. Signed-off-by:
Moudy Ho <moudy.ho@mediatek.com> Reviewed-by:
CK Hu <ck.hu@mediatek.com> Link: https://lore.kernel.org/r/20220610063424.7800-6-moudy.ho@mediatek.com [mb: fix commit subject] Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and DT schema expects certain pattern with 'led'. Use generic color properties instead of the node name. Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by:
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Krzysztof Kozlowski authored
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by:
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Chunfeng Yun authored
Enable USB remote wakeup of all four xHCI controller Reviewed-by:
Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by:
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Chunfeng Yun authored
Add efuse node and cells used by t-phy to fix the bit shift issue Reviewed-by:
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Roger Lu authored
Add compatible/reg/irq/clock/efuse setting in svs node. Signed-off-by:
Roger Lu <roger.lu@mediatek.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20220516004311.18358-3-roger.lu@mediatek.comSigned-off-by:
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- 07 Jun, 2022 3 commits
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Rex-BC Chen authored
Add mediatek,cci property to support MediaTek CCI feature. Signed-off-by:
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Rex-BC Chen authored
Add MediaTek CCI devfreq node for MT8183. Signed-off-by:
Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> Signed-off-by:
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Rex-BC Chen authored
- Add cpufreq opp table. - Add MediaTek cci opp table. - Add property of opp table and clock fro cpufreq. Signed-off-by:
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