- 05 Jan, 2024 4 commits
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Jani Nikula authored
Display code should not care about graphics version. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240104174350.823605-4-jani.nikula@intel.com
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Jani Nikula authored
Display code should not care about graphics version. While at it, abstract the version check to a separate macro. Signed-off-by:
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Jani Nikula authored
Display code should not care about graphics version. Signed-off-by:
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Jani Nikula authored
Display code should not care about graphics version. Signed-off-by:
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- 04 Jan, 2024 5 commits
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Imre Deak authored
MST connectors don't have a static attached encoder, as their encoder can change depending on the pipe they use; so the encoder for an MST connector can't be retrieved using intel_dp_attached_encoder() (which may return NULL for MST). Most of the PSR debugfs entries depend on a static connector -> encoder mapping which is only true for eDP and SST DP connectors and not for MST. These debugfs entries were enabled for MST connectors as well recently to provide PR information for them, but handling MST connectors needs more changes. Fix this by not adding for now the PSR entries on MST connectors. To make things more uniform add the entries for SST connectors on all platforms, not just on platforms supporting DP2.0. v2: - Keep adding the entries for SST connectors. (Jouni) - Add a TODO: comment for MST support. Fixes: ef75c25e ("drm/i915/panelreplay: Debugfs support for panel replay") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9850 Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240103152609.2434100-1-imre.deak@intel.com
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Mika Kahola authored
PLL's are not programmed in case of fastset so the state verification compares bios programmed PLL values against sw PLL values. To overcome this limitation, we can skip the state verification for C10 in fastset case as the driver is not writing PLL values. Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219123246.832245-1-mika.kahola@intel.com
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Mika Kahola authored
The function intel_c20_use_mplla() is not really widely used and can be replaced with the more suitable pll->tx[0] & C20_PHY_USE_MPLLB expression. Let's remove the intel_c20_use_mplla() alltogether and replace mplla/mpllb selection by checking mpllb bit. Signed-off-by:
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Mika Kahola authored
We can calculate the hw port clock during the hw readout and store it as pll_state->clock for C20 state verification. In order to do that we need to move intel_c20pll_calc_port_clock() function. Signed-off-by:
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Mika Kahola authored
Add pll selection check for C20 as well as clock state verification0. We have been relying on sw state to select A or B pll's. This is incorrect as the hw might see this selection differently. This patch fixes this shortcoming by reading pll selection for both sw and hw states and compares if these two selections match. Fixes: 59be9024 ("drm/i915/mtl: C20 state verification") v2: reword commit message and include fix to a original commit (Imre) Compare pll selection (Jani) Signed-off-by:
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- 03 Jan, 2024 1 commit
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Haridhar Kalvala authored
Correct the implementation trying to detect MTL PCH with the MTL fake PCH id. On MTL, both the North Display (NDE) and South Display (SDE) functionality reside on the same die (the SoC die in this case), unlike many past platforms where the SDE was on a separate PCH die. The code is (badly) structured today in a way that assumes the SDE is always on the PCH for modern platforms, so on platforms where we don't actually need to identify the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows us to avoid restructuring a bunch of the code.we've been assigning a "fake PCH" as a quick hack that allows us to avoid restructuring a bunch of the code. Removed unused macros of LNL amd MTL as well. v2: Reorder PCH_MTL conditional check (Matt Roper) Reverting to PCH_MTL for PICA interrupt(Matt Roper) Signed-off-by:Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by:
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- 29 Dec, 2023 1 commit
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Jani Nikula authored
Remove some unused declarations probably left behind after some refactoring. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231221105414.1518267-1-jani.nikula@intel.com
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- 22 Dec, 2023 8 commits
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Jouni Högander authored
We need to configure VSC Select field in video dip ctl if we want to have e.g. colorimetry date in our VSC SDP. Signed-off-by:
Shawn Lee <shawn.c.lee@intel.com> Reviewed-by:
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Jouni Högander authored
VSC SDP sending is taken care by PSR HW and it's not enabled in VIDEO_DIP_CTL when PSR is enabled. Readback of VSC SDP is depending on VSC_SDP being set in intel_crtc_state->infoframes.enabled. In case of PSR setting this flag is taken care by PSR code -> read back PSR configuration before reading VSC SDP otherwise we get pipeconfig mismatch error. Signed-off-by:
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Jouni Högander authored
Pipe config check is currently ignoring vsc sdp changes completely if psr is enabled. We want to ignore only PSR part of it as there might be changes in colorimetry data. Also read back vsc_sdp when psr is used. Signed-off-by:
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Jouni Högander authored
Currently colorimetry data is not added for psr1 or non-psr case. Fix this by adding it as needed. Signed-off-by:
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Jouni Högander authored
There is no specific reason to prepare VSC SDP for PSR case somehow differently. Unify PSR and non-PSR preparation. Signed-off-by:
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Jouni Högander authored
Colorimetry support is not really a PSR specific thing. Move it to intel_dp struct and use it also when preparing vsc sdp for non-PSR case. Signed-off-by:
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Jouni Högander authored
There is no really need to have separate vsc for psr usage. Use intel_crtc_state->infoframes.vsc instead. Signed-off-by:
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Suraj Kandpal authored
Fail repeater authentication step in case RX_INFO indicates HDCP1.x or HDCP2.0/2.1 device is present downstream in repeater topology and content type set by userspace is Type1. --v2 -Fix build error. --v3 -remove mst encoder check as branch device also act as repeater Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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- 20 Dec, 2023 1 commit
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Gustavo Sousa authored
The cdclk tables were introduced with commit 736da811 ("drm/i915: Use literal representation of cdclk tables"). It has been almost 4 years and the divider field was not really used yet. Let's remove it. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
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- 19 Dec, 2023 7 commits
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Khaled Almahallawy authored
Using link_status to get DPCD_REV fails when disabling/defaulting phy pattern. Use intel_dp->dpcd to access DPCD_REV correctly. Fixes: 8cdf7271 ("drm/i915/dp: Program vswing, pre-emphasis, test-pattern") Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by:
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Khaled Almahallawy authored
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: rebase v3: - Enable TPS4 only for supported platforms (Jani) - Uppercase in macro names (Jani) - Fix indentation (Jani) - Use drm_warn instead of WARN v4: Disable TPS4 pattern on supported platforms only Bspec: 50482, 50484, 7557 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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Khaled Almahallawy authored
Starting from DP2.0 specs, DPCD 248h is renamed LINK_QUAL_PATTERN_SELECT and it has the same values of registers DPCD 10Bh-10Eh. Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add CP2520 Pattern 3 (TPS4) phy pattern support in the next patch of this series and DP2.1 PHY patterns for future series. v2: rebase Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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Nirmoy Das authored
Test like i915_gem_mman_live_selftests/igt_mmap_migrate can cause dmesg spamming. Use ratelimit api to reduce log rate. References: https://gitlab.freedesktop.org/drm/intel/-/issues/7038Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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Nirmoy Das authored
Add a function for ratelimitted debug print. Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Acked-by:
Maxime Ripard <mripard@kernel.org> Signed-off-by:
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Jani Nikula authored
intel_hdcp_get_repeater_ctl() is supposed to return unsigned register contents. Returning negative error values is unexpected, and none of the callers check for that. Sort of fix the error cases by returning 0. I don't think we should hit these cases anyway, and using 0 for the registers is safer than 0xffffffea (-EINVAL). Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231219104746.1065431-2-jani.nikula@intel.com
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Jani Nikula authored
It's customary to debug log connectors using [CONNECTOR:%d:%s] format. Make the HDCP code follow suit. Signed-off-by:
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- 18 Dec, 2023 5 commits
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Jouni Högander authored
After switching to directly using dma_fence instead of i915_sw_fence we have left some dead code around intel_atomic_helper->free_list. Remove that dead code. v2: Remove intel_atomic_state->freed as well Signed-off-by:
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Ville Syrjälä authored
To help with debugging print out the mmio list contained in the DMC firmware. Also highlight the event registers, and whether we're going to disable them or not. Signed-off-by:
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Ville Syrjälä authored
Unlike later platforms TGL/ADLS has the half refresh rate (HRR) event on the main DMC (as opposed to the pipe DMC). Since we're disabling that event on all later platforms already let's do the same on TGL/ADLS as well. There is supposedly a bit somewhere (DMC_CHICKEN on TGL) to make the handler not do anything, but we don't currently have code to frob it. Though that bit should be off by default, the ADL+ experience has shown us that trusting any of this isn't a good idea. So seems safer to just disable all event handlers we know that we don't need. Also the TGL/ADLS DMC firmware is apparently using the wrong event (undelayed vblank) here anyway. It should be using the delayed vblank event instead (like ADL+ firmware does), but they didn't release a firmware fix for this and instead just hacked around this in the Windows driver code :/ v2: Also disable the event on ADLS (Imre) Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Ville Syrjälä authored
Unlike later platforms TGL has its flip queue event (CLK_MSEC) on the main DMC (as opposed to the pipe DMC). Currently we're doing a second pass to disable that, but let's just follow the same approach as the later platforms and never even enable the event in the first place. Signed-off-by:
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Ville Syrjälä authored
The pipe DMC seems to be making a mess of things in ADL. Various weird symptoms have been observed such as missing vblank irqs, typicalle happening when using multiple displays. Keep all pipe DMC event handlers disabled until needed (which is never atm). This is also what Windows does on ADL+. We can also drop DG2 from disable_all_flip_queue_events() since on DG2 the pipe DMC is the one that handles the flip queue events. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8685Signed-off-by:
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- 15 Dec, 2023 1 commit
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Imre Deak authored
Select the HDMI specific PLL clock only for HDMI outputs. Fixes: 62618c7f ("drm/i915/mtl: C20 PLL programming") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
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- 13 Dec, 2023 7 commits
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Ville Syrjälä authored
Drop the redundant dev_priv parameters from intel_ddi_compute_min_voltage_level() to make life easier. Signed-off-by:
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Ville Syrjälä authored
On MTL we need to bump the voltage level to only 1 (not 2) when port clock exceeds 594MHz. Make it so. Signed-off-by:
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Ville Syrjälä authored
The mess inside intel_ddi_compute_min_voltage_level() is illegible. Clean it up a bit by splitting the internals into per-platform functions. TODO: make it a vfunc? Signed-off-by:
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Ville Syrjälä authored
Allow MTL to use voltage level 1 for 480MHz cdclk, instead of the voltage level 2 that it's currently using. Signed-off-by:
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Ville Syrjälä authored
The cdclk->voltage_level if ladders are hard to read, especially as they're written the other way around compared to how bspec lists the limits. Let's rewrite them to use simple arrays that gives us the max cdclk for each voltage level. v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to accommodate JSL machines in CI that boot with high cdclk Reviewed-by: -
Ville Syrjälä authored
Currently we have a hardcoded assumption that the cdclk divider (2*cd2x divider) is always 2 when squashing is used. While that is true for all current platforms it might not hold in the future. So eliminate the assumption and calculate the correct divider from the other parameters. v2: s/cd2x divider/cdclk divider/ (Gustavo) s/clock/unsquashed_cdclk/ (Gustavo) Reviewed-by: -
Ville Syrjälä authored
Replace the slightly magic 'size = 16' with a bit more descriptive name. We'll have another user for this value later on. Signed-off-by:
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