- 29 May, 2024 26 commits
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Rajneesh Bhardwaj authored
On GFXIP9.4.3, make CPX mode as the default compute mode if the node is setup in NPS4 memory partition mode. This change is only applicable for dGPU, for APU, continue to use TPX mode. Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Set up pipe1 as a high priority queue. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Use correct ref/mask for differnent gfx ring pipe. Ported from ZhenGuo's patch for gfx10. Reviewed-by:
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Victor Skvortsov authored
flush_gpu_tlb may be called from another thread while device_gpu_recover is running. Both of these threads access registers through the VF RLCG interface during VF Full Access. Add a lock around this interface to prevent race conditions between these threads. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
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Alex Deucher authored
With commit 89773b85 ("drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs") big and small APU "VRAM" handling in KFD was unified. Since AMD_IS_APU is set for both big and small APUs, we can simplify the checks in the code. v2: clean up a few more places (Lang) Acked-by:
Lang Yu <Lang.Yu@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 28ebbb49. Revert this commit as apparently the LLVM code to take advantage of this never landed. Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Allocate some memory, send the address in chunks to dmub, and finally ask it to copy the bounding box data into the newly allocated memory. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Aurabindo Pillai authored
New commands for enabling copy of DC bounding box values from VBIOS DMUB Signed-off-by:
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Aurabindo Pillai authored
Move creation of CGS device node and the DAL allocation list from amdgpu_dm_init() to dm_sw_init() which runs before dmub's sw init hook. This is required for communicating with the VBIOS DMUB image from the VBIOS that was loaded for early pre-os boot. Signed-off-by:
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Rodrigo Siqueira authored
Add some additional registers. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Aurabindo Pillai authored
When ODM slice happens on DCN401, there is a null pointer exception caused by that. This commit address this issue by checking if the required data structures are initialized. Reviewed-by:
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Aurabindo Pillai authored
All the DC_FP_START/END should be used before call anything from DML2, for this reason, the use of those guards inside DML it is not correct. This commit removes two unnecessary DC_FP_START/END from a dml2 function. Reviewed-by:
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Aurabindo Pillai authored
DCN401 is using DCN 320 headers, which does not have all the right registers for DCN401. This commit just replace DCN320 includes with the one from DCN410. Reviewed-by:
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Aurabindo Pillai authored
Drop the extra HPD irq entry for DCN401. Reviewed-by:
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Rodrigo Siqueira authored
Most of the DML code is generated, and it is necessary to update some parts of it from time to time. This commit brings the latest generated code for DML 2.1. Signed-off-by:
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Pinninti authored
[why] cleaning up the code refactor requires hubp to be in its own component. [how] move all files under newly created hubp folder and fixing the makefiles. Reviewed-by:
Pinninti <bpinnint@amd.com> Acked-by:
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Rodrigo Siqueira authored
This commit removes some unused code with the required adjustments. Signed-off-by:
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Samson Tam authored
[Why] Enable sharpener support for DCN401 [How] - Removed memcmp check that was preventing ISHARP from being enabled. - Add missing ISHARP register defines, masks, and writes. - Add programming of Blur and Scale coefficients. - Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel - format - Only enable ISHARP for YUV420 - Add disabling of ISHARP - Add debug flags and registry keys for debugging ISHARP. - Set default to medium level Acked-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Sridevi authored
[Why] Incorrect cursor position calculation in some scenarios. Also for mirror and rotation cases. [How] Fix for incorrect cursor position. Added new test scenarios for diags cursor test. Updated CRC for few of the diags cursor test scenarios. Reviewed-by:
Sridevi <sarvinde@amd.com> Acked-by:
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Yang Wang authored
fix typo "info.ue_count" in amdgpu_ras_aca_sysfs_read() function. Fixes: 865d3397 ("drm/amdgpu: add aca deferred error type support") Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Jesse Zhang authored
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent. To make the code more robust, check the pointer parent. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by:
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David (Ming Qiang) Wu authored
AMD_PG_SUPPORT_VCN_DPG is needed for secure parts and should/can be enabled by now. Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Reviewed-by:
Sonny Jiang <sonjiang@amd.com> Signed-off-by:
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Alex Deucher authored
It was an enablement vehicle for MES 11 and was never productized. Remove it. v2: drop additional checks in the GFX10 code. v3: drop mes_api_def.h Acked-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Jiapeng Chong authored
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5200 dc_power_down_on_boot() warn: inconsistent indenting. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9166Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Convert a variable sized array from [1] to []. Reviewed-by:
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Alex Deucher authored
Use current speed/width on devices which don't support dynamic PCIe switching. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3289Acked-by:
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- 23 May, 2024 14 commits
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Mario Limonciello authored
MST colorspace property support was disabled due to a series of warnings that came up when the device was plugged in since the properties weren't made at device creation. Create the properties in advance instead. Suggested-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: 69a95961 ("drm/amd/display: Temporary Disable MST DP Colorspace Property"). Reported-and-tested-by:
Tyler Schneider <tyler.schneider@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
The fix involves adding a null check for 'stream' at the beginning of the function. If 'stream' is NULL, the function immediately returns false. This ensures that 'stream' is not NULL when we dereference it to access 'ctx' in 'dc = stream->ctx->dc;' the function. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:398 dc_stream_program_cursor_position() error: we previously assumed 'stream' could be null (see line 397) drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c 389 bool dc_stream_program_cursor_position( 390 struct dc_stream_state *stream, 391 const struct dc_cursor_position *position) 392 { 393 struct dc *dc; 394 bool reset_idle_optimizations = false; 395 const struct dc_cursor_position *old_position; 396 397 old_position = stream ? &stream->cursor_position : NULL; ^^^^^^^^ The patch adds a NULL check --> 398 dc = stream->ctx->dc; ^^^^^^^^ The old code didn't check 399 400 if (dc_stream_set_cursor_position(stream, position)) { 401 dc_z10_restore(dc); 402 403 /* disable idle optimizations if enabling cursor */ 404 if (dc->idle_optimizations_allowed && 405 (!old_position->enable || dc->debug.exit_idle_opt_for_cursor_updates) && 406 position->enable) { 407 dc_allow_idle_optimizations(dc, false); Fixes: f63f86b5 ("drm/amd/display: Separate setting and programming of cursor") Reported-by:Dan Carpenter <dan.carpenter@linaro.org> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Sunil Khatri authored
Add support of all the CP GFX queues for gfx11 ipdump to be used by devcoredump. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Sunil Khatri authored
Add gfx11 support of CP queue registers for all queues to be used by devcoredump. Reviewed-by:
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Mario Limonciello authored
Errors in amdgpu_dm_init() are silently ignored and dm_hw_init() will succeed. However often these are fatal errors and it would be better to pass them up. Reviewed-by:
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Sunil Khatri authored
Add support of gfx11 ipdump print so devcoredump could trigger it to dump the captured registers in devcoredump. Reviewed-by:
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Sunil Khatri authored
Add general registers of gfx11 in ipdump for devcoredump support. Reviewed-by:
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Sunil Khatri authored
IB1 registers: regCP_IB1_CMD_BUFSZ regCP_IB1_BASE_LO regCP_IB1_BASE_HI regCP_IB1_BUFSZ regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR Above registers are part of the asic but not of the offset file for gc_11_0_0_offset.h and hence adding them. Reviewed-by:
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Sunil Khatri authored
Adding more device information: a. PCI info b. VRAM and GTT info c. GDC config Also correct the print layout and section information for in devcoredump. Reviewed-by:
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Sunil Khatri authored
add prints before and after ip state is dumped. It avoids user to think of system being stuck/hung as dump could take some time after a gpu hang. Reviewed-by:
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Sunil Khatri authored
Add gfx queue register for all instances in devcoredump for gfx10. Reviewed-by:
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Sunil Khatri authored
Add support to dump registers of all instances of cp queue registers of gfx10 to devcoredump. Reviewed-by:
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Sunil Khatri authored
Rename the memory pointer from ip_dump to ip_dump_core to make it specific to core registers and rest other registers to be dumped in their respective memories. Reviewed-by:
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Lijo Lazar authored
KFD uses crc16 for gpu_id generation. Fixes: 3ed181b8 ("drm/amdkfd: Ensure gpu_id is unique") Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202405211405.TidTWIBX-lkp@intel.com/Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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