- 19 Apr, 2022 4 commits
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Darren Powell authored
Clarify the smu_cmn_send_smc_msg_with_param documentation to mention two cases exist where messages are silently dropped with no error returned. These cases occur in unusual situations where either: 1. the message type is not allowed to a virtual GPU, or 2. a PCI recovery is underway and the HW is not yet in sync with the SW For more details see commit 4ea5081c ("drm/amd/powerplay: enable SMC message filter") commit bf36b52e ("drm/amdgpu: Avoid accessing HW when suspending SW state") (v2) Reworked with suggestions from Luben & Paul (v3) Updated wording as per Luben's feedback Corrected error stating all messages denied on virtual GPU (each GPU has mask of which messages are allowed) Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
It needs to check if the pp_funcs is initialized while release the context, otherwise it will trigger null pointer panic while the software smu is not enabled. [ 1109.404555] BUG: kernel NULL pointer dereference, address: 0000000000000078 [ 1109.404609] #PF: supervisor read access in kernel mode [ 1109.404638] #PF: error_code(0x0000) - not-present page [ 1109.404657] PGD 0 P4D 0 [ 1109.404672] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 1109.404701] CPU: 7 PID: 9150 Comm: amdgpu_test Tainted: G OEL 5.16.0-custom #1 [ 1109.404732] Hardware name: innotek GmbH VirtualBox/VirtualBox, BIOS VirtualBox 12/01/2006 [ 1109.404765] RIP: 0010:amdgpu_dpm_force_performance_level+0x1d/0x170 [amdgpu] [ 1109.405109] Code: 5d c3 44 8b a3 f0 80 00 00 eb e5 66 90 0f 1f 44 00 00 55 48 89 e5 41 57 41 56 41 55 41 54 53 48 83 ec 08 4c 8b b7 f0 7d 00 00 <49> 83 7e 78 00 0f 84 f2 00 00 00 80 bf 87 80 00 00 00 48 89 fb 0f [ 1109.405176] RSP: 0018:ffffaf3083ad7c20 EFLAGS: 00010282 [ 1109.405203] RAX: 0000000000000000 RBX: ffff9796b1c14600 RCX: 0000000002862007 [ 1109.405229] RDX: ffff97968591c8c0 RSI: 0000000000000001 RDI: ffff9796a3700000 [ 1109.405260] RBP: ffffaf3083ad7c50 R08: ffffffff9897de00 R09: ffff979688d9db60 [ 1109.405286] R10: 0000000000000000 R11: ffff979688d9db90 R12: 0000000000000001 [ 1109.405316] R13: ffff9796a3700000 R14: 0000000000000000 R15: ffff9796a3708fc0 [ 1109.405345] FS: 00007ff055cff180(0000) GS:ffff9796bfdc0000(0000) knlGS:0000000000000000 [ 1109.405378] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1109.405400] CR2: 0000000000000078 CR3: 000000000a394000 CR4: 00000000000506e0 [ 1109.405434] Call Trace: [ 1109.405445] <TASK> [ 1109.405456] ? delete_object_full+0x1d/0x20 [ 1109.405480] amdgpu_ctx_set_stable_pstate+0x7c/0xa0 [amdgpu] [ 1109.405698] amdgpu_ctx_fini.part.0+0xcb/0x100 [amdgpu] [ 1109.405911] amdgpu_ctx_do_release+0x71/0x80 [amdgpu] [ 1109.406121] amdgpu_ctx_ioctl+0x52d/0x550 [amdgpu] [ 1109.406327] ? _raw_spin_unlock+0x1a/0x30 [ 1109.406354] ? drm_gem_handle_delete+0x81/0xb0 [drm] [ 1109.406400] ? amdgpu_ctx_get_entity+0x2c0/0x2c0 [amdgpu] [ 1109.406609] drm_ioctl_kernel+0xb6/0x140 [drm] Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Lang Yu authored
The idea is from commit a50fe707 ("drm/amdkfd: Only apply heavy-weight TLB flush on Aldebaran") and commit f61c40c0 ("drm/amdkfd: enable heavy-weight TLB flush on Arcturus"). At the moment, heavy-weight TLB could cause problems on ASICs except Aldebaran and Arcturus. A simple hipMallocManaged/hipFree program could trigger this issue. [ 97.787657] amdgpu 0000:01:00.0: amdgpu: wait for kiq fence error: 0. [ 106.868758] amdgpu: qcm fence wait loop timeout expired [ 106.868966] amdgpu: The cp might be in an unrecoverable state due to an unsuccessful queues preemption [ 106.869203] amdgpu: Failed to evict process queues [ 106.869261] amdgpu: Failed to quiesce KFD Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Lang Yu authored
To make kfd_flush_tlb_after_unmap visible in kfd_svm.c, move it into kfd_priv.h. And change it to an inline function. Signed-off-by:
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- 14 Apr, 2022 5 commits
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Gavin Wan authored
[why] These static variables save the RLC Scratch registers address. When we install multiple GPUs (for example: XGMI setting) and multiple GPUs call the function at same time. The RLC Scratch registers address are changed each other. Then it caused reading/writing from/to wrong GPU. [how] Removed the static from the variables. The variables are on the stack. Fixes: 5d447e29 ("drm/amdgpu: add helper for rlcg indirect reg access") Reviewed-by:
Gavin Wan <Gavin.Wan@amd.com> Signed-off-by:
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Felix Kuehling authored
Add the waiters to the wait queue during initialization, while holding the event spinlock. Otherwise the waiter will not get activated if the event signals before being added to the wait queue. Signed-off-by:
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Rodrigo Siqueira authored
This reverts commit 863fa85e. While we were testing DCN3.1 with a hub, we noticed that only one of 2 connected displays lights up when using some specific display resolution. In summary, this was the setup: 1. Displays: * Sharp LQ156M1JW26 (eDP): 1080@240 * BENQ SW320 (DP): 4k@60 * BENQ EX3203R (DP): 4k@60 2. Hub: Club3D CSV-7300 3. ASIC: DCN3.1 After bisecting this issue, we figured out the commit mentioned above introduced this issue. We are investigating why this patch introduced this regression, but we need to revert it for now. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Mark Broadworth <Mark.Broadworth@amd.com> Cc: Michael Strauss <michael.strauss@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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xinhui pan authored
VM might already be freed when amdgpu_vm_tlb_seq_cb() is called. We see the calltrace below. Fix it by keeping the last flush fence around and wait for it to signal BUG kmalloc-4k (Not tainted): Poison overwritten 0xffff9c88630414e8-0xffff9c88630414e8 @offset=5352. First byte 0x6c instead of 0x6b Allocated in amdgpu_driver_open_kms+0x9d/0x360 [amdgpu] age=44 cpu=0 pid=2343 __slab_alloc.isra.0+0x4f/0x90 kmem_cache_alloc_trace+0x6b8/0x7a0 amdgpu_driver_open_kms+0x9d/0x360 [amdgpu] drm_file_alloc+0x222/0x3e0 [drm] drm_open+0x11d/0x410 [drm] Freed in amdgpu_driver_postclose_kms+0x3e9/0x550 [amdgpu] age=22 cpu=1 pid=2485 kfree+0x4a2/0x580 amdgpu_driver_postclose_kms+0x3e9/0x550 [amdgpu] drm_file_free+0x24e/0x3c0 [drm] drm_close_helper.isra.0+0x90/0xb0 [drm] drm_release+0x97/0x1a0 [drm] __fput+0xb6/0x280 ____fput+0xe/0x10 task_work_run+0x64/0xb0 Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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Dan Carpenter authored
If lookup_event_by_id() returns a NULL "ev" pointer then the spin_lock(&ev->lock) will crash. This was detected by Smatch: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.c:644 kfd_set_event() error: we previously assumed 'ev' could be null (see line 639) Fixes: 5273e82c ("drm/amdkfd: Improve concurrency of event handling") Signed-off-by:Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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- 13 Apr, 2022 6 commits
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Mukul Joshi authored
Currently, the IO-links to the device being removed from topology, are not cleared. As a result, there would be dangling links left in the KFD topology. This patch aims to fix the following: 1. Cleanup all IO links to the device being removed. 2. Ensure that node numbering in sysfs and nodes proximity domain values are consistent after the device is removed: a. Adding a device and removing a GPU device are made mutually exclusive. b. The global proximity domain counter is no longer required to be an atomic counter. A normal 32-bit counter can be used instead. 3. Update generation_count to let user-mode know that topology has changed due to device removal. CC: Shuotao Xu <shuotaoxu@microsoft.com> Reviewed-by:Shuotao Xu <shuotaoxu@microsoft.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Yongqiang Sun authored
MS_HYPERV with vega10 doesn't have the interface to process request init data msg. Check hypervisor type to not send the request for MS_HYPERV. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Alice Wong <shiwei.wong@amd.com> Acked-by:
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Lang Yu authored
A MAX_GPU_INSTANCE bits bitmap will suffice. Signed-off-by:
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Wenjing Liu authored
[why] Extract update stream allocation table into link hwss as part of the link hwss refactor work. Reviewed-by:
George Shen <George.Shen@amd.com> Reviewed-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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David Zhang authored
[why] creating a generic helper for AMD specific PSR-SU sink validation. Moving the function to the power module to reference it across all OS. [how] - drop PSRSU specific sink validation helper and move to power module by reading PSR version and other PSR caps - call the new helper from linux DM (amdgpu_dm_psr) Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
David Zhang <dingchen.zhang@amd.com> Signed-off-by:
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David Zhang authored
[why & how] As per eDP 1.5 spec, add the below two DPCD bit fields for PSR-SU support and capability: 1. DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 2. DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED changes in v2 ------------------ * fixed the typo * explicitly list what DPCD bit fields are added Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- 12 Apr, 2022 15 commits
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Aric Cyr authored
Title: DC Patches Apri 6, 2022 This DC patchset brings improvements in multiple areas. In summary, we highlight: *Disabling Z10 on DCN31 *Fix issue breaking 32bit Linux build *Fix inconsistent timestamp type *Add DCN30 support FEC init *Fix crash on setting VRR with no display connected *Disable FEC if DSC not supported for EDP *Add odm seamless boot support *Select correct DTO source *Power down hardware if timer not trigger Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] Change criteria for setting DTO source value, and always set it regardless of the signal type. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Felix Kuehling authored
The synchronize_rcu call in destroy_events can take several ms, which noticeably slows down applications destroying many events. Use kfree_rcu to free the event structure asynchronously and eliminate the synchronize_rcu call in the user thread. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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hersen wu authored
[Why] within dc link detecion, dp link training will be executed for external sst dp. for debug purpose, we may need skip dp link training. [How] expose dc debug option to skip_detection_link_training to debugfs Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
hersen wu <hersenxs.wu@amd.com> Signed-off-by:
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Dillon Varone authored
Reviewed-by:
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Angus Wang authored
[WHY] An unsigned int timestamp variable is assigned with an unsigned long long value. Also, the assignment directly converts the tick value to us without using built-in get elapsed time function. [HOW] Cast the assigned value correctly and also use built-in function to get the timestamp in the unit we want. v2: squash in 64 bit division fix Reviewed-by:
Angus Wang <Angus.Wang@amd.com> Signed-off-by:
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Jingwen Zhu authored
[Why] FEC init used on DCN30. [How] Check fec active when HW init. Co-authored-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Reviewed-by:
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Duncan Ma authored
[WHY] Implement changes to transition from Pre-OS odm to Post-OS odm support. Seamless boot case is also considered. [HOW] Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has odm enabled. Reset odm and det size when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Duncan Ma <Duncan.Ma@amd.com> Signed-off-by:
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Oliver Logush authored
[why] Need to update the update_clock sequence to a fully tested sequence for dcn30 [how] Removed the check to see if clock is lowered Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Oliver Logush <oliver.logush@amd.com> Signed-off-by:
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Oliver Logush authored
[why] Make sure smu is not busy before sending another request, this is to prevent stress failures from MS. [how] Check to make sure the SMU fw busy signal is cleared before sending another request Reviewed-by:
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Paul Hsieh authored
[WHY] In headless systems, if SetMode/Power down timer is not called, hardware will not be powered down causing HW/SW discrepancies. Powering down hardware on SetPowerState to D3 will ensure SW/HW state is accurate. [HOW] 1. If PowerDownThread timer is not trigger but OS call SetPowerState to D3, power down hardware. 2. Update HDMI hang w/a to apply to all TMDS signals on headless system Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Paul Hsieh <paul.hsieh@amd.com> Signed-off-by:
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Charlene Liu authored
[why] dcn316's dtbclk is from non_ss clock source. no compensation required here. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Evgenii Krasnikov authored
[HOW&WHY] Make sure psr_force_static() can always be called regardless of psr_allow_active value. Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Reviewed-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Reviewed-by:
Nicholas Choi <Nicholas.Choi@amd.com> Acked-by:
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Harry VanZyllDeJong authored
[HOW&WHY] VRR was getting set at the same time the timing generator would be null when there was no display connected. Added null check to the timing generator variable so it does not get referenced if it is null. Reviewed-by:
Harry VanZyllDeJong <hvanzyll@amd.com> Signed-off-by:
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Iswara Nagulendran authored
[WHY] Screen was seen corrupted for a few ms when switching both ways. There was also not enough bandwidth for HDR to be enabled in HG disabled mode. This was due to FEC being enabled although DSC was not supported or disabled for the EDP. [HOW] Check for EDP DSC support in DC caps or if DSC should be disabled for EDP before enabling FEC for EDP. Reviewed-by:
Iswara Nagulendran <inagulen@amd.com> Signed-off-by:
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- 11 Apr, 2022 10 commits
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Tom Rix authored
The only use of the global variables in r600_blit_shaders.c were in the old drivers/gpu/drm/radeon/r600_blit.c This file was removed in commit 8333f607 ("drm/radeon: remove UMS support") So remove the r600_blit_shaders.[c|h] files Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Max Erenberg authored
[WHY] The dGPU cannot enter PSR when it is not connected to a panel. [HOW] Added a check to dc_link_set_psr_allow_active which returns early if panel is disconnected. Reviewed-by:
Max Erenberg <merenber@amd.com> Signed-off-by:
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Saaem Rizvi authored
[WHY] Z10 is should not be enabled by default on DCN31. [HOW] Using DC debug flags to disable Z10 by default on DCN31. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Saaem Rizvi <syerizvi@amd.com> Signed-off-by:
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Josip Pavic authored
[Why] When booting, the driver waits for the MPC idle bit to be set as part of pipe initialization. However, on some systems this occurs before OTG is enabled, and since the MPC idle bit won't be set until the vupdate signal occurs (which requires OTG to be enabled), this never happens and the wait times out. This can add hundreds of milliseconds to the boot time. [How] Do not wait for mpc idle if tg is disabled Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
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Eric Yang authored
[Why] Z10 and S0i3 have some shared path. Previous code clean up , incorrectly removed these pointers, which breaks s0i3 restore [How] Do not clear the function pointers based on Z10 disable. Reviewed-by:
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Stanley.Yang authored
In order to debug ras error, driver will print IPID/SYND/MISC0 register value if detect correctable or uncorrectable error. Provide umc_query_error_status_helper function to reduce code redundancy. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Use div_u64() rather than a a 64 bit divide. Fixes: 3fe5739d ("drm/amd/display: Add flip interval workaround") Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Grigory Vasilyev authored
Instead of the 'amdgpu_ring_priority_level' type, the 'amdgpu_gfx_pipe_priority' type was used, which is an error when setting ring priority. This is a minor error, but may cause problems in the future. Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3, but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the code. Signed-off-by:
Grigory Vasilyev <h0tc0d3@gmail.com> Signed-off-by:
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Tom Rix authored
cayman_default_state and cayman_default_size are only used in ni.c. Single file symbols should be static. So move their definitions to cayman_blit_shaders.h and change their storage-class-specifier to static. Remove unneeded cayman_blit_shader.c cayman_ps/vs definitions were removed with commit 4f862967 ("drm/radeon/kms: remove r6xx+ blit copy routines") So their declarations in cayman_blit_shader.h are not needed, so remove them. Signed-off-by:
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Tom St Denis authored
The data revision was not changed to 5 from 4 when the CG flags were extended to 64-bits. Since this was missed I took the opportunity to add future upper 64-bits of PG flags as well so we don't need to bump it again when that comes. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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