- 21 Oct, 2023 22 commits
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Stephan Gerhold authored
Enable sound and modem for the Samsung A2015 based devices (A3, A5, E5, E7, Grand Max). The setup is similar to most MSM8916 devices, i.e.: - QDSP6 audio - Earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX except: - NXP TFA9895 codec for speaker on Quaternary MI2S - Samsung-specific audio jack detection (not supported yet) [Lin: Add e2015 and grandmax] Co-developed-by:
"Lin, Meng-Bo" <linmengbo0689@protonmail.com> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20231003-msm8916-modem-v2-5-61b684be55c0@gerhold.netSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Stephan Gerhold authored
Most MSM8916/MSM8939 devices use very similar setups for the modem, because most of the device-specific details are abstracted by the modem firmware. There are several definitions (status switches, DAI links etc) that will be exactly the same for every board. Introduce a common msm8916-modem-qdsp6.dtsi include that can be used to simplify enabling the modem for such devices. By default the digital/analog codec in the SoC/PMIC is used, but boards can define additional codecs by adding additional backend DAI links. Signed-off-by:
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Stephan Gerhold authored
MSM8939 does not have a dedicated ADSP. Instead, the audio services via APR are also implemented by the modem DSP. Audio can be either routed via the modem DSP (necessary for voice call audio etc) or directly sent to the LPASS hardware (currently used by DB410c). Bypassing QDSP6 audio is only possible with special firmware (on DB410c) or when the modem DSP is completely disabled. Add the typical nodes for QDSP6 audio to msm8939.dtsi. The apr node is disabled by default to avoid changing behavior for devices like apq8039-t2 that use the bypassed audio path. Signed-off-by:
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Stephan Gerhold authored
MSM8916 does not have a dedicated ADSP. Instead, the audio services via APR are also implemented by the modem DSP. Audio can be either routed via the modem DSP (necessary for voice call audio etc) or directly sent to the LPASS hardware (currently used by DB410c). Bypassing QDSP6 audio is only possible with special firmware (on DB410c) or when the modem DSP is completely disabled. Add the typical nodes for QDSP6 audio to msm8916.dtsi. The apr node is disabled by default to avoid changing behavior for devices like DB410c that use the bypassed audio path. Signed-off-by:
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Vincent Knecht authored
BAM DMUX is used as the network interface to the modem. This is copied as-is from msm8916.dtsi. Signed-off-by:
Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Johan Hovold authored
Add the missing pin configuration for the recently added camera indicator LED. Fixes: 1c63dd1c ("arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED") Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231003093647.3840-1-johan+linaro@kernel.orgSigned-off-by:
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Luca Weiss authored
Use gpio@ instead of pinctrl@ as that's the name expected by the qcom,spmi-pmic.yaml schema. Update it to fix dt validation. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231002-pm7250b-gpio-fixup-v2-2-debb8b599989@fairphone.comSigned-off-by:
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Luca Weiss authored
Add the CCI busses found on sc7280 and their pinctrl states. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Joel Selvaraj authored
Configure and enable the dual-tone on the PocoPhone F1 Signed-off-by:
Joel Selvaraj <joelselvaraj.oss@gmail.com> Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by:
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Caleb Connolly authored
Both the 6 and 6T feature a dual tone flash, enable it. Signed-off-by:
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Konrad Dybcio authored
The DP PHY needs different settings when an eDP display is used. Make sure these apply on the X13s. FWIW I could not notice any user-facing change stemming from this commit. Fixes: f48c70b1 ("arm64: dts: qcom: sc8280xp-x13s: enable eDP display") Signed-off-by:
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Stephan Gerhold authored
Fix a couple of instances of incorrectly sorted nodes in the MSM8916 boards. They should be ordered alphabetically for consistency. No functional change. Signed-off-by:
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Stephan Gerhold authored
Enable &wcnss_mem for msm8939-longcheer-l9100. This is needed now to have WCNSS working. It was missed when &wcnss_mem was disabled by default because the patch with the msm8939-longcheer-l9100 device tree was not applied yet. Fixes: 0ece6438 ("arm64: dts: qcom: msm8916/39: Disable unneeded firmware reservations") Signed-off-by:
André Apitzsch <git@apitzsch.eu> Tested-by:
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Stephan Gerhold authored
Enable the GPU for the msm8916-samsung-gt58 and gt510 tablets now that they have display panels enabled in the device tree. This was missed when the GPU was disabled by default because the change was not applied yet. Fixes: 0ce5bb82 ("arm64: dts: qcom: msm8916/39: Disable GPU by default") Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
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Varadarajan Narayanan authored
IPQ95xx SoCs have different OPPs available for the CPU based on SoC variant. This can be determined from an eFuse register present in the silicon. Add support to read the eFuse and populate the OPPs based on it. Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw Limit ------------------------------------------------------------ 936000000 1 1 1 1 0xf 1104000000 1 1 1 1 0xf 1200000000 1 1 1 1 0xf 1416000000 0 1 1 1 0x7 1488000000 0 1 1 1 0x7 1800000000 0 1 0 1 0x5 2208000000 0 0 0 1 0x1 ----------------------------------------------------------- Reviewed-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.comSigned-off-by:
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Varadarajan Narayanan authored
IPQ53xx have different OPPs available for the CPU based on SoC variant. This can be determined through use of an eFuse register present in the silicon. Add support to read the eFuse and populate the OPPs based on it. ------------------------------------------------ Frequency BIT2 BIT1 opp-supported-hw 1.1GHz 1.5GHz ------------------------------------------------ 1100000000 1 1 0x7 1500000000 0 1 0x3 ------------------------------------------------ Signed-off-by:
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Richard Acayan authored
The bindings for the CPU frequency scaling driver require a specific compatible for the SoC. Add the compatible. Fixes: 0c665213 ("arm64: dts: qcom: sdm670: add cpu frequency scaling") Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
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Dmitry Baryshkov authored
Follow the example of other platforms and extend the PDC resource region to 0x30000, so that the PDC driver can read the PDC_VERSION register. Fixes: 397ad946 ("arm64: dts: qcom: sm8150: Add pdc interrupt controller node") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230929-topic-sm8x50-upstream-pdc-ver-v5-2-800111572104@linaro.orgSigned-off-by:
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- 16 Oct, 2023 17 commits
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Robert Marko authored
Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Caleb Connolly authored
The rb2 only has a single USB controller, it can be switched between a type-c port and an internal USB hub via a DIP switch. Until dynamic role switching is available it's preferable to put the USB controller in host mode so that the type-A ports and ethernet are available. Signed-off-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Fixes: eaa53a85 ("arm64: dts: qcom: qrb4210-rb2: Enable USB node") Reviewed-by:
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Priyansh Jain authored
Add tsens and thermal devicetree node for sa8775p SoC. Signed-off-by:
Priyansh Jain <quic_priyjain@quicinc.com> Link: https://lore.kernel.org/r/20230926085948.23046-3-quic_priyjain@quicinc.comSigned-off-by:
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Raghavendra Kakarla authored
Add device node for sleep stats driver which provides various low power mode stats. Tested-by:
Andrew Halaney <ahalaney@redhat.com> Signed-off-by:
Raghavendra Kakarla <quic_rkakarla@quicinc.com> Reviewed-by:
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Luca Weiss authored
Add the USB3+DP Combo QMP PHY port subnodes to facilitate the description of the connection between the hardware blocks. Put it in the SoC DTSI to avoid duplication in the device DTs. Reviewed-by:
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Konrad Dybcio authored
To make dtbs_check happy and the software more aware of what's going on, describe the HSUSB PHY's regulators and tighten up VDDA_PLL to match. Signed-off-by:
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Konrad Dybcio authored
Enable the onboard QCA Wi-Fi. HW identifiers for reference: qmi chip_id 0x320 chip_family 0x4001 board_id 0xff soc_id 0x400e0000 Firmware sources: /vendor/firmware_mnt/image/wlanmdsp.bin -> qcom/.../wlanmdsp.mbn /vendor/firmware_mnt/image/bdwlan.bXX [1] -> [2] -> ath10k/.../board-2.bin [3] -> ath10k/.../firmware-5.bin Not sure where 3 comes from on the device itself, gotta investigate that.. According to [4], it's called WCN3990_STRAIT. Enable it and tighten the relevant regulators. [1] XX = board_id printed when the file is missing or by your downstream kernel firmware loader in the dmesg; if XX=ff, use bdwlan.bin [2] https://github.com/jhugo/linux/blob/5.5rc2_wifi/README [3] https://github.com/kvalo/ath10k-firmware/blob/master/WCN3990/hw1.0/HL3.1/WLAN.HL.3.1-01040-QCAHLSWMTPLZ-1/firmware-5.bin [4] https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/qca-wifi-host-cmn/-/blob/LA.VENDOR.1.0.r1-20700-WAIPIO.QSSI13.0/hif/src/hif_hw_version.h#L55Signed-off-by: -
Konrad Dybcio authored
Enable the 5G modem on the Sony Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Add UART1 node, generally used for the Bluetooth module. Signed-off-by:
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Anusha Rao authored
Add support for wps buttons on GPIO 37. Reviewed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
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Anusha Rao authored
Add a dtsi file to include interfaces that are common across RDPs. Signed-off-by:
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Nitheesh Sekar authored
Enable USB2 in host mode. Reviewed-by:
Amandeep Singh <quic_amansing@quicinc.com> Signed-off-by:
Nitheesh Sekar <quic_nsekar@quicinc.com> Link: https://lore.kernel.org/r/20230904063635.24975-5-quic_nsekar@quicinc.comSigned-off-by:
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Nitheesh Sekar authored
Add USB phy and controller nodes. Co-developed-by:
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Om Prakash Singh authored
The sc7280 SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by:
Om Prakash Singh <quic_omprsing@quicinc.com> Link: https://lore.kernel.org/r/20231015193901.2344590-5-quic_omprsing@quicinc.com [bjorn: Padded address to 8 digits, moved hunk to maintain sort order] Signed-off-by:
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Om Prakash Singh authored
The sa8775p SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by:
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Neil Armstrong authored
The SM8450 SoC has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20231003-topic-sm8550-rng-v4-5-255e4d0ba08e@linaro.orgSigned-off-by:
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Neil Armstrong authored
Add the Qualcomm True Random Number Generator node. Reviewed-by:
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- 27 Sep, 2023 1 commit
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Stephan Gerhold authored
Add the missing regulator supplies to the ADV7533 HDMI bridge to fix the following dtbs_check warnings. They are all also supplied by pm8916_l6 so there is no functional difference. apq8016-sbc.dtb: bridge@39: 'dvdd-supply' is a required property apq8016-sbc.dtb: bridge@39: 'pvdd-supply' is a required property apq8016-sbc.dtb: bridge@39: 'a2vdd-supply' is a required property from schema display/bridge/adi,adv7533.yaml Fixes: 28546b09 ("arm64: dts: apq8016-sbc: Add HDMI display support") Signed-off-by:
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