- 30 Jun, 2023 36 commits
-
-
Alvin Lee authored
[Description] - Previous implementation didn't consider multiple surfaces in a flip - Loop through each surface in each flip to ensure the update path is correct Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Austin Zheng authored
[Why] K1 and K2 not being setting properly when subVP is active. [How] Have phantom pipes use the same programing as the main pipes without checking the paired stream Cc: stable@vger.kernel.org Tested-by:
Austin Zheng <austin.zheng@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] - We want to limit the new fast update path to address and gamma updates only. - Add a check in dc_update_planes_and_stream to only take the new fast update path if we only have the specific fast updates defined. Tested-by:
Jun Lei <jun.lei@amd.com> Acked-by:
-
Harry Wentland authored
The shaper LUT requires a 10-bit value of the delta between segments. We were using dc_fixpt_clamp_u0d10() to do that but it doesn't do what we want it to do. It will preserve 10-bit precision after the decimal point, but that's not quite what we want. We want 14-bit precision and discard the 4 most-significant bytes. To do that we'll do dc_fixpt_clamp_u0d14() & 0x3ff instead. Tested-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
-
Lijo Lazar authored
When PSP block is not present, use direct programming. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Mangesh Gadre <Mangesh.Gadre@amd.com> Tested-by:
-
Melissa Wen authored
If shaper and 3D LUT data updates, lut_3d bit in update_flag is updated and we need to call set_input_transfer_func to program DPP shaper and 3D LUTs. Small cleanup of code style in the related if-condition. Tested-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
-
Hersen Wu authored
This change causes regression when eDP and external display in mirror mode. When external display supports low resolution than eDP, use eDP timing to driver external display may cause corruption on external display. This reverts commit e749dd10. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2655Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
-
James Zhu authored
To save render node resoure, share drm device setting for pci amdgpu device with 1st XCP partition device. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Lijo Lazar authored
Expose unique id of GFX v9.4.3 ASICs as device attribute. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
-
Lijo Lazar authored
on APUs with GFX v9.4.3 Signed-off-by:
-
Emily Deng authored
Need to unpause dpg first, or it will hit follow error during stop dpg: "[drm] Register(1) [regUVD_POWER_STATUS] failed to reach value 0x00000001 != 0x00000000n" Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
-
Le Ma authored
Handled in earlier phase Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
-
YiPeng Chai authored
Fatal error occurs in ras poison mode, mode1 reset is used to recover gpu. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
-
Alex Deucher authored
It's required for high priority queues. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2535Reviewed-and-tested-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
-
Alex Deucher authored
So we can selectively enable it on certain devices. No intended functional change. Reviewed-and-tested-by:
-
Mario Limonciello authored
PSP functions are already set by psp_early_init() so initializing them a second time is unnecessary. No intended functional changes. Signed-off-by:
-
Mario Limonciello authored
This reverts commit 072030b1. This is no longer necessary when using newer DMUB F/W. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
-
Mario Limonciello authored
The same parade TCON issue can potentially happen on Phoenix, and the same PSR resilience changes have been ported into the DMUB firmware. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Signed-off-by:
-
Mario Limonciello authored
A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443Signed-off-by:
-
Mario Limonciello authored
The `DMUB_FW_VERSION` macro has a mistake in that the revision field is off by one byte. The last byte is typically used for other purposes and not a revision. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by:
-
Evan Quan authored
The feature mask bit was not correctly cleared. Without that, the L2H and H2L interrupts cannot be enabled. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
-
Hong-lu Cheng authored
[why] Endless assert caused by LinesInDETChroma=0. [how] Don't floor for LinesInDETChroma=0 Tested-by:
Hong-lu Cheng <hong-lu.cheng@amd.com> Signed-off-by:
-
Ilya Bakoulin authored
[Why] This display doesn't properly indicate link loss through DPCD bits such as CR_DONE / CHANNEL_EQ_DONE / SYMBOL_LOCKED / INTERLANE_ALIGN_DONE, which all remain set. In addition, DPCD200Eh doesn't match the value of DPCD204h in all cases. For these reasons, we can miss re-training the link, since we don't properly detect link loss with this display. [Why] Add display-specific workaround to read DPCD204h, so that we can detect link loss based on 128b132b-specific status bits in this register. Tested-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by:
-
Zhigang Luo authored
port SRIOV VF missed changes from gfx_v9_0 to gfx_v9_4_3. Reviewed-by:
Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by:
-
Mario Limonciello authored
If the securedisplay TA failed to load the first time, it's unlikely to work again after a suspend/resume cycle or reset cycle and it appears to be causing problems in futher attempts. Fixes: e42dfa66 ("drm/amdgpu: Add secure display TA load for Renoir") Reported-by:
Filip Hejsek <filip.hejsek@gmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2633Signed-off-by:
-
Mukul Joshi authored
For GFX 9.4.3, interrupt handling needs to be updated for: - Interrupt cookie will have a NodeId field. Each KFD node needs to check the NodeId before processing the interrupt. - For CPX mode, there are additional checks of client ID needed to process the interrupt. - Add NodeId to the process drain interrupt. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Christian König authored
Since adding gang submit we need to take the gang size into account while reserving fences. Signed-off-by:
-
Hamza Mahfooz authored
Currently, it is possible for us to access memory that we shouldn't. Since, we acquire (possibly dangling) pointers to dirty rectangles before doing a bounds check to make sure we can actually accommodate the number of dirty rectangles userspace has requested to fill. This issue is especially evident if a compositor requests both MPO and damage clips at the same time, in which case I have observed a soft-hang. So, to avoid this issue, perform the bounds check before filling a single dirty rectangle and WARN() about it, if it is ever attempted in fill_dc_dirty_rect(). Cc: stable@vger.kernel.org # 6.1+ Fixes: 30ebe415 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
-
Lijo Lazar authored
Publish energy data in 15.625mJ unit for SMU v13.0.6. The same unit is used in Aldebaran also. Signed-off-by:
-
Lijo Lazar authored
Modify it such that it doesn't change the instance mask parameter. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Signed-off-by:
-
Mangesh Gadre authored
sdma halt/unhalt is performed by psp when frontdoor loading used,so this can be skipped. v2: Instead of removing halt/unhalt completely, driver will do it only during backdoor load. Signed-off-by:Asad Kamal <asad.kamal@amd.com> Signed-off-by:
-
Tao Zhou authored
No RAS irq is allowed. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
-
Kenneth Feng authored
add abnormal fan detection for smu 13.0.0 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
-
Xiaogang Chen authored
Since we allow kfd and graphic operate on same GPU VM to have interoperation between them GPU VM may have been used by graphic vm operations before kfd turns a GPU VM into a compute VM. Remove vm clean checking at amdgpu_vm_make_compute. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
-
Mario Limonciello authored
A number of users have reported that there are random hangs occurring caused by PSR-SU specifically on panels that contain the parade 0803 TCON. Users have been able to work around the issue by disabling PSR entirely. To avoid these hangs, disable PSR-SU when this TCON is found. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Suggested-by:
Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443Signed-off-by:
-
Mukul Joshi authored
Enable GWS capable queue creation for forward progress gaurantee on GFX 9.4.3. Signed-off-by:
-
- 23 Jun, 2023 4 commits
-
-
Evan Quan authored
It is proved that insufficient LC_L1_INACTIVITY setting can cause audio noise on some platform. With the LC_L1_INACTIVITY increased to 4ms, the issue can be resolved. Signed-off-by:
-
Aric Cyr authored
This version brings along the following: - DCN314 fixes - DCN32x fixes - New fast update sequence enablement - DC mode clock switching enablement for DCN32x - DP link loss fix - New debugfs entry to set MST link settings Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
-
Alvin Lee authored
- DC mode clock switch interface was previously only executed for DCN303. Enable it for DCN32x so that the interface is called correctly - Assign function pointers for DCN32x that are used in the dc mode interface - Update the dc mode interface to work generically for each ASIC - In update_clocks, make sure to consider softmax if we're in DC mode Reviewed-by:
-
Ilya Bakoulin authored
[Why] We don't check 128b132b-specific bits in LANE_ALIGN_STATUS_UPDATED DPCD registers when parsing link loss status, which can cause us to miss a link loss notification from some sinks. [How] Add a 128b132b-specific status bit check. Cc: stable@vger.kernel.org # 6.3+ Reviewed-by:
-
