1. 28 Feb, 2018 3 commits
    • Eugeniy Paltsev's avatar
      ARC: mcip: update MCIP debug mask when the new cpu came online · f3205de9
      Eugeniy Paltsev authored
      As of today we use hardcoded MCIP debug mask, so if we launch
      kernel via debugger and kick fever cores than HW has all cpus
      hang at the momemt of setup MCIP debug mask.
      
      So update MCIP debug mask when the new cpu came online, instead of
      use hardcoded MCIP debug mask.
      Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      f3205de9
    • Eugeniy Paltsev's avatar
      ARC: mcip: halt GFRC counter when ARC cores halt · 07423d00
      Eugeniy Paltsev authored
      In SMP systems, GFRC is used for clocksource. However by default the
      counter keeps running even when core is halted (say when debugging via a
      JTAG debugger). This confuses Linux timekeeping and triggers flase RCU stall
      splat such as below:
      
      | [ARCLinux]# while true; do ./shm_open_23-1.run-test ; done
      | Running with 1000 processes for 1000 objects
      | hrtimer: interrupt took 485060 ns
      |
      | create_cnt: 1000
      | Running with 1000 processes for 1000 objects
      | [ARCLinux]# INFO: rcu_preempt self-detected stall on CPU
      |       2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0
      | INFO: rcu_preempt detected stalls on CPUs/tasks:
      | 	0-...: (1 GPs behind) idle=71e/0/0 softirq=135264/135264 fqs=0
      |	2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0
      |	3-...: (1 GPs behind) idle=4e0/0/0 softirq=134304/134304 fqs=0
      |	(detected by 1, t=13648 jiffies, g=31493, c=31492, q=1)
      
      Starting from ARC HS v3.0 it's possible to tie GFRC to state of up-to 4
      ARC cores with help of GFRC's CORE register where we set a mask for
      cores which state we need to rely on.
      
      We update cpu mask every time new cpu came online instead of using
      hardcoded one or using mask generated from "possible_cpus" as we
      want it set correctly even if we run kernel on HW which has fewer cores
      than expected (or we launch kernel via debugger and kick fever cores
      than HW has)
      
      Note that GFRC halts when all cores have halted and thus relies on
      programming of Inter-Core-dEbug register to halt all cores when one
      halts.
      Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
      Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      [vgupta: rewrote changelog]
      07423d00
    • Vineet Gupta's avatar
      ARCv2: boot log: fix HS48 release number · 701eda01
      Vineet Gupta authored
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      701eda01
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