1. 24 Sep, 2024 10 commits
    • Huacai Chen's avatar
      Docs/LoongArch: Add advanced extended IRQ model description · f339bd3b
      Huacai Chen authored
      Introduce the advanced extended interrupt controllers (AVECINTC). This
      feature will allow each core to have 256 independent interrupt vectors
      and MSI interrupts can be independently routed to any vector on any CPU.
      
      The whole topology of irqchips in LoongArch machines looks like this if
      AVECINTC is supported:
      
        +-----+     +-----------------------+     +-------+
        | IPI | --> |        CPUINTC        | <-- | Timer |
        +-----+     +-----------------------+     +-------+
                     ^          ^          ^
                     |          |          |
              +---------+ +----------+ +---------+     +-------+
              | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
              +---------+ +----------+ +---------+     +-------+
                   ^            ^
                   |            |
              +---------+  +---------+
              | PCH-PIC |  | PCH-MSI |
              +---------+  +---------+
                ^     ^           ^
                |     |           |
        +---------+ +---------+ +---------+
        | Devices | | PCH-LPC | | Devices |
        +---------+ +---------+ +---------+
                         ^
                         |
                    +---------+
                    | Devices |
                    +---------+
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      Signed-off-by: default avatarTianyang Zhang <zhangtianyang@loongson.cn>
      f339bd3b
    • Xi Ruoyao's avatar
      LoongArch: Remove posix_types.h include from sigcontext.h · 64c35d6c
      Xi Ruoyao authored
      Nothing in sigcontext.h seems to require anything from
      linux/posix_types.h.  This include seems a MIPS relic originated from
      an error in Linux 2.6.11-rc2 (in 2005).
      
      The unneeded include was found debugging some vDSO self test build
      failure (it's not the root cause though).
      
      Link: https://lore.kernel.org/linux-mips/20240828030413.143930-2-xry111@xry111.site/
      Link: https://lore.kernel.org/loongarch/0b540679ec8cfccec75aeb3463810924f6ff71e6.camel@xry111.site/Signed-off-by: default avatarXi Ruoyao <xry111@xry111.site>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      64c35d6c
    • Wentao Guan's avatar
      LoongArch: Fix memleak in pci_acpi_scan_root() · 5016c3a3
      Wentao Guan authored
      Add kfree(root_ops) in this case to avoid memleak of root_ops,
      leaks when pci_find_bus() != 0.
      Signed-off-by: default avatarYuli Wang <wangyuli@uniontech.com>
      Signed-off-by: default avatarWentao Guan <guanwentao@uniontech.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      5016c3a3
    • Uros Bizjak's avatar
      LoongArch: Simplify _percpu_read() and _percpu_write() · d4f31acf
      Uros Bizjak authored
      Now _percpu_read() and _percpu_write() macros call __percpu_read()
      and __percpu_write() static inline functions that result in a single
      assembly instruction. However, percpu infrastructure expects its leaf
      definitions to encode the size of their percpu variable, so the patch
      merges all the asm clauses from the static inline function into the
      corresponding leaf macros.
      
      The secondary effect of this change is to avoid explicit __percpu
      annotations for function arguments. Currently, __percpu macro is defined
      in include/linux/compiler_types.h, but with proposed patch [1], __percpu
      definition will need macros from include/asm-generic/percpu.h, creating
      forward dependency loop.
      
      The proposed solution is the same as x86 architecture uses.
      
      [1] https://lore.kernel.org/lkml/20240812115945.484051-4-ubizjak@gmail.com/Tested-by: default avatarXi Ruoyao <xry111@xry111.site>
      Signed-off-by: default avatarUros Bizjak <ubizjak@gmail.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      d4f31acf
    • Huacai Chen's avatar
      LoongArch: Improve hardware page table walker · f93f67d0
      Huacai Chen authored
      LoongArch has similar problems explained in commit 7f0b1bf0
      ("arm64: Fix barriers used for page table modifications"), when hardware
      page table walker (PTW) enabled, speculative accesses may cause spurious
      page fault in kernel space. Theoretically, in order to completely avoid
      spurious page fault we need a "dbar + ibar" pair between the page table
      modifications and the subsequent memory accesses using the corresponding
      virtual address. But "ibar" is too heavy for performace, so we only use
      a "dbar 0b11000" in set_pte(). And let spurious_fault() filter the rest
      rare spurious page faults which should be avoided by "ibar".
      
      Besides, we replace the llsc loop with amo in set_pte() which has better
      performace, and refactor mmu_context.h to 1) avoid any load/store/branch
      instructions between the writing of CSR.ASID & CSR.PGDL, 2) ensure flush
      tlb operation is after updating ASID.
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      f93f67d0
    • Huacai Chen's avatar
      LoongArch: Add ARCH_HAS_SET_DIRECT_MAP support · f04de6d8
      Huacai Chen authored
      Add set_direct_map_*() functions for setting the direct map alias for
      the page to its default permissions and to an invalid state that cannot
      be cached in a TLB. (See d253ca0c ("x86/mm/cpa: Add set_direct_map_*()
      functions")) Add a similar implementation for LoongArch.
      
      This fixes the KFENCE warnings during hibernation:
      
       ==================================================================
       BUG: KFENCE: invalid read in swsusp_save+0x368/0x4d8
      
       Invalid read at 0x00000000f7b89a3c:
        swsusp_save+0x368/0x4d8
        hibernation_snapshot+0x3f0/0x4e0
        hibernate+0x20c/0x440
        state_store+0x128/0x140
        kernfs_fop_write_iter+0x160/0x260
        vfs_write+0x2c0/0x520
        ksys_write+0x74/0x160
        do_syscall+0xb0/0x160
      
       CPU: 0 UID: 0 PID: 812 Comm: bash Tainted: G    B              6.11.0-rc1+ #1566
       Tainted: [B]=BAD_PAGE
       Hardware name: Loongson-LS3A5000-7A1000-1w-CRB, BIOS vUDK2018-LoongArch-V2.0.0 10/21/2022
       ==================================================================
      
      Note: We can only set permissions for KVRANGE/XKVRANGE kernel addresses.
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      f04de6d8
    • Huacai Chen's avatar
      LoongArch: Add ARCH_HAS_SET_MEMORY support · e86935f7
      Huacai Chen authored
      Add set_memory_ro/rw/x/nx architecture hooks to change the page
      attribution.
      
      Use own set_memory.h rather than generic set_memory.h (i.e.
      include/asm-generic/set_memory.h), because we want to add other function
      prototypes here.
      
      Note: We can only set attributes for KVRANGE/XKVRANGE kernel addresses.
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      e86935f7
    • Jiaxun Yang's avatar
      LoongArch: Rework CPU feature probe from CPUCFG/IOCSR · 34e3c450
      Jiaxun Yang authored
      Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
      resilience to different core implementations.
      
      BTW, IOCSR register definition appears to be a platform-specific spec
      instead of an architecture spec, even for the Loongson CPUs there is no
      guarantee that IOCSR will always present.
      
      Thus it's dangerous to perform IOCSR probing without checking CPU type
      and instruction availability.
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      34e3c450
    • Bibo Mao's avatar
      LoongArch: Enable ACPI BGRT handling · d0bb0b60
      Bibo Mao authored
      Add ACPI BGRT support on LoongArch so it can display image provied by
      acpi table at boot stage and switch to graphical UI smoothly.
      Signed-off-by: default avatarBibo Mao <maobibo@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      d0bb0b60
    • Tiezhu Yang's avatar
      LoongArch: Enable generic CPU vulnerabilites support · e8dd556c
      Tiezhu Yang authored
      Currently, many architectures support generic CPU vulnerabilites, such
      as x86, arm64 and riscv:
      
       commit 61dc0f55 ("x86/cpu: Implement CPU vulnerabilites sysfs functions")
       commit 61ae1321 ("arm64: enable generic CPU vulnerabilites support")
       commit 0e3f3649 ("riscv: Enable generic CPU vulnerabilites support")
      
      All LoongArch CPUs (since Loongson-3A5000) implement a special mechanism
      in the processor core to prevent "Meltdown" and "Spectre" attacks, so it
      can enable generic CPU vulnerabilites support for LoongArch too.
      
      Without this patch, there are no user interfaces of vulnerabilities to
      check on LoongArch. The output of those files reflects the state of the
      CPUs in the system, the output value "Not affected" means "CPU is not
      affected by the vulnerability".
      
      Before:
      
       # cat /sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow
       cat: /sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow: No such file or directory
       # cat /sys/devices/system/cpu/vulnerabilities/spec_store_bypass
       cat: /sys/devices/system/cpu/vulnerabilities/spec_store_bypass: No such file or directory
       # cat /sys/devices/system/cpu/vulnerabilities/meltdown
       cat: /sys/devices/system/cpu/vulnerabilities/meltdown: No such file or directory
      
      After:
      
       # cat /sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow
       Not affected
       # cat /sys/devices/system/cpu/vulnerabilities/spec_store_bypass
       Not affected
       # cat /sys/devices/system/cpu/vulnerabilities/meltdown
       Not affected
      
      Link: https://www.loongson.cn/EN/news/show?id=633Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      e8dd556c
  2. 17 Sep, 2024 5 commits
    • Tiezhu Yang's avatar
      LoongArch: Remove STACK_FRAME_NON_STANDARD(do_syscall) · 0eb0bd21
      Tiezhu Yang authored
      For now, we can remove STACK_FRAME_NON_STANDARD(do_syscall) because
      there is no objtool warning "do_syscall+0x11c: return with modified
      stack frame", then there is handle_syscall() which is the previous
      frame of do_syscall() in the call trace when executing the command
      "echo l > /proc/sysrq-trigger".
      
      Fixes: a0f7085f ("LoongArch: Add RANDOMIZE_KSTACK_OFFSET support")
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      0eb0bd21
    • Tiezhu Yang's avatar
      LoongArch: Set AS_HAS_THIN_ADD_SUB as y if AS_IS_LLVM · a7e08377
      Tiezhu Yang authored
      When building kernel with "make CC=clang defconfig", LLVM Assembler is
      used due to LLVM_IAS=0 is not specified, then AS_HAS_THIN_ADD_SUB is not
      set, thus objtool can not be built after enable it for Clang.
      
      config AS_HAS_THIN_ADD_SUB is to check whether -mthin-add-sub option is
      available to know R_LARCH_{32,64}_PCREL are supported for GNU Assembler,
      there is no such an option for LLVM Assembler. The minimal version of
      Clang is 18 for building LoongArch kernel, and Clang >= 17 has already
      supported R_LARCH_{32,64}_PCREL, that is to say, there is no need to
      depend on AS_HAS_THIN_ADD_SUB for Clang, so just set AS_HAS_THIN_ADD_SUB
      as y if AS_IS_LLVM.
      
      Fixes: 120dd411 ("LoongArch: Only allow OBJTOOL & ORC unwinder if toolchain supports -mthin-add-sub")
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      a7e08377
    • Tiezhu Yang's avatar
      LoongArch: Enable objtool for Clang · b8468bd9
      Tiezhu Yang authored
      For now, it can enable objtool for Clang, just remove !CC_IS_CLANG for
      HAVE_OBJTOOL in arch/loongarch/Kconfig.
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      b8468bd9
    • Tiezhu Yang's avatar
      objtool: Handle frame pointer related instructions · da5b2ad1
      Tiezhu Yang authored
      After commit a0f7085f ("LoongArch: Add RANDOMIZE_KSTACK_OFFSET
      support"), there are three new instructions "addi.d $fp, $sp, 32",
      "sub.d $sp, $sp, $t0" and "addi.d $sp, $fp, -32" for the secondary
      stack in do_syscall(), then there is a objtool warning "return with
      modified stack frame" and no handle_syscall() which is the previous
      frame of do_syscall() in the call trace when executing the command
      "echo l > /proc/sysrq-trigger".
      
      objdump shows something like this:
      
      0000000000000000 <do_syscall>:
         0:   02ff8063        addi.d          $sp, $sp, -32
         4:   29c04076        st.d            $fp, $sp, 16
         8:   29c02077        st.d            $s0, $sp, 8
         c:   29c06061        st.d            $ra, $sp, 24
        10:   02c08076        addi.d          $fp, $sp, 32
        ...
        74:   0011b063        sub.d           $sp, $sp, $t0
        ...
        a8:   4c000181        jirl            $ra, $t0, 0
        ...
        dc:   02ff82c3        addi.d          $sp, $fp, -32
        e0:   28c06061        ld.d            $ra, $sp, 24
        e4:   28c04076        ld.d            $fp, $sp, 16
        e8:   28c02077        ld.d            $s0, $sp, 8
        ec:   02c08063        addi.d          $sp, $sp, 32
        f0:   4c000020        jirl            $zero, $ra, 0
      
      The instruction "sub.d $sp, $sp, $t0" changes the stack bottom and the
      new stack size is a random value, in order to find the return address of
      do_syscall() which is stored in the original stack frame after executing
      "jirl $ra, $t0, 0", it should use fp which points to the original stack
      top.
      
      At the beginning, the thought is tended to decode the secondary stack
      instruction "sub.d $sp, $sp, $t0" and set it as a label, then check this
      label for the two frame pointer instructions to change the cfa base and
      cfa offset during the period of secondary stack in update_cfi_state().
      This is valid for GCC but invalid for Clang due to there are different
      secondary stack instructions for ClangBuiltLinux on LoongArch, something
      like this:
      
      0000000000000000 <do_syscall>:
        ...
        88:   00119064        sub.d           $a0, $sp, $a0
        8c:   00150083        or              $sp, $a0, $zero
        ...
      
      Actually, it equals to a single instruction "sub.d $sp, $sp, $a0", but
      there is no proper condition to check it as a label like GCC, and so the
      beginning thought is not a good way.
      
      Essentially, there are two special frame pointer instructions which are
      "addi.d $fp, $sp, imm" and "addi.d $sp, $fp, imm", the first one points
      fp to the original stack top and the second one restores the original
      stack bottom from fp.
      
      Based on the above analysis, in order to avoid adding an arch-specific
      update_cfi_state(), we just add a member "frame_pointer" in the "struct
      symbol" as a label to avoid affecting the current normal case, then set
      it as true only if there is "addi.d $sp, $fp, imm". The last is to check
      this label for the two frame pointer instructions to change the cfa base
      and cfa offset in update_cfi_state().
      
      Tested with the following two configs:
      (1) CONFIG_RANDOMIZE_KSTACK_OFFSET=y &&
          CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=n
      (2) CONFIG_RANDOMIZE_KSTACK_OFFSET=y &&
          CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
      
      By the way, there is no effect for x86 with this patch, tested on the
      x86 machine with Fedora 40 system.
      
      Cc: stable@vger.kernel.org # 6.9+
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      da5b2ad1
    • Huacai Chen's avatar
      Merge tag 'irq-core-2024-09-16' into loongarch-next · 987cbafe
      Huacai Chen authored
      LoongArch architecture changes for 6.12 depend on the irq core
      changes about AVEC irqchip to avoid confliction, so merge them
      to create a base.
      987cbafe
  3. 15 Sep, 2024 3 commits
    • Linus Torvalds's avatar
      Linux 6.11 · 98f7e32f
      Linus Torvalds authored
      98f7e32f
    • Linus Torvalds's avatar
      Merge tag 'for-linus-6.11' of git://git.kernel.org/pub/scm/virt/kvm/kvm · d42f7708
      Linus Torvalds authored
      Pull kvm fix from Paolo Bonzini:
       "Do not always honor guest PAT on CPUs that support self-snoop.
      
        This triggers an issue in the bochsdrm driver, which used ioremap()
        instead of ioremap_wc() to map the video RAM.
      
        The revert lets video RAM use the WB memory type instead of the slower
        UC memory type"
      
      * tag 'for-linus-6.11' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
        Revert "KVM: VMX: Always honor guest PAT on CPUs that support self-snoop"
      d42f7708
    • Paolo Bonzini's avatar
      Revert "KVM: VMX: Always honor guest PAT on CPUs that support self-snoop" · 9d70f3fe
      Paolo Bonzini authored
      This reverts commit 377b2f35.
      
      This caused a regression with the bochsdrm driver, which used ioremap()
      instead of ioremap_wc() to map the video RAM.  After the commit, the
      WB memory type is used without the IGNORE_PAT, resulting in the slower
      UC memory type.  In fact, UC is slow enough to basically cause guests
      to not boot... but only on new processors such as Sapphire Rapids and
      Cascade Lake.  Coffee Lake for example works properly, though that might
      also be an effect of being on a larger, more NUMA system.
      
      The driver has been fixed but that does not help older guests.  Until we
      figure out whether Cascade Lake and newer processors are working as
      intended, revert the commit.  Long term we might add a quirk, but the
      details depend on whether the processors are working as intended: for
      example if they are, the quirk might reference bochs-compatible devices,
      e.g. in the name and documentation, so that userspace can disable the
      quirk by default and only leave it enabled if such a device is being
      exposed to the guest.
      
      If instead this is actually a bug in CLX+, then the actions we need to
      take are different and depend on the actual cause of the bug.
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      9d70f3fe
  4. 14 Sep, 2024 4 commits
  5. 13 Sep, 2024 11 commits
  6. 12 Sep, 2024 7 commits