- 17 Jan, 2014 5 commits
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Tero Kristo authored
The OMAP clock driver now supports DPLL clock type. This patch also adds support for DT DPLL nodes. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Tero Kristo authored
ti_dt_clk_init_provider() can now be used to initialize the contents of a single clock IP block. This parses all the clocks under the IP block and calls the corresponding init function for them. This patch also introduces a helper function for the TI clock drivers to get register info from DT and append the master IP info to this. Signed-off-by:
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Tero Kristo authored
Some devices require their clocks to be available with a specific dev-id con-id mapping. With DT, the clocks can be found by default only with their name, or alternatively through the device node of the consumer. With drivers, that don't support DT fully yet, add mechanism to register specific clock names. Signed-off-by:
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Tero Kristo authored
SOC_DRA7XX was under wrong menu within Kconfig file, which prevented DRA7XX only build. Fixed the kconfig options for this SoC as we are there. voltage.c needs to be added to the DRA7XX build also, otherwise DRA7XX only build will fail. Signed-off-by:
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Tero Kristo authored
DRA7XX and AM43XX were missing common clock code from the Makefile, which causes build breakage in DRA7XX / AM43XX only builds once clock support for these SoCs is added. Add the missing entries to the Makefile as preparation of this. Signed-off-by:
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- 16 Jan, 2014 16 commits
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Mike Turquette authored
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Stephen Boyd authored
Document the multimedia clock controller found on Qualcomm devices Cc: <devicetree@vger.kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Stephen Boyd authored
Document the global clock controller found on Qualcomm devices. Cc: <devicetree@vger.kernel.org> Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM8660 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the multimedia clock controller found on MSM 8960 based platforms. This should allow multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM8960 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by:
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Stephen Boyd authored
Signed-off-by:
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Stephen Boyd authored
Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by:
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Stephen Boyd authored
Add support for Qualcomm's PLLs (phase locked loops). This is sufficient enough to be able to determine the rate the PLL is running at. We can add rate setting support later when it's needed. Signed-off-by:
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Stephen Boyd authored
Add a clock type that associates a regmap pointer and some enable/disable bits with a clk_hw struct. This will be the struct that a hw specific implementation wraps if it wants to use the regmap helper functions. Signed-off-by:
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Stephen Boyd authored
Some of Qualcomm's clocks can change their parent and rate at the same time with a single register write. Add support for this hardware to the common clock framework by adding a new set_rate_and_parent() op. When the clock framework determines that both the parent and the rate are going to change during clk_set_rate() it will call the .set_rate_and_parent() op if available and fall back to calling .set_parent() followed by .set_rate() otherwise. Reviewed-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Stephen Boyd authored
If a user of <linux/reset-controller.h> doesn't include <linux/of.h> before including reset-controller.h they'll get a warning as follows: include/linux/reset-controller.h:44:17: warning: 'struct of_phandle_args' declared inside parameter list This is because of_phandle_args is not forward declared. Add the declaration to silence this warning. Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Barry Song authored
sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for prima2 and atlas6, there are many shared clocks but there are still some different register layout and hardware clocks, then result in different clock table. here we re-arch the driver to 1. clk-common.c provides common clocks for prima2 and atlas6, 2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides prima2 specific clocks and clock table. 3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides atlas6 specific clocks and clock table. 4. clk.h and clk.c expose external interfaces and provide uniform entry for both prima2 and atlas6. so both prima2 and atlas6 will get support by drivers/clk/sirf. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by:
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- 15 Jan, 2014 1 commit
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Mike Turquette authored
The composite clock's .determine_rate implementation can call the underyling .determine_rate callback corresponding to rate_hw or the underlying .determine_rate callback corresponding to mux_hw. In both cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into the correct callback. Reported-by:
Lemon Dai <dailemon.gl@gmail.com> Signed-off-by:
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- 14 Jan, 2014 3 commits
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Mike Turquette authored
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Valentine Barshak authored
The clks member of the clk_onecell_data structure should point to a valid clk array (no NULL entries allowed), and the clk_num should be equal to the number of elements in the clks array. The MSTP driver fails to satisfy the above conditions. The clks array may contain NULL entries if not all clock-indices are initialized in the device tree. Thus, if the clock indices are interleaved we end up with NULL pointers in-between. The other problem is the driver uses maximum clock index as the number of clocks, which is incorrect (less than the actual number of clocks by 1). Fix the first issue by pre-setting the whole clks array with ERR_PTR(-ENOENT) pointers instead of zeros; and use maximum clkidx + 1 as the number of clocks to fix the other one. This should make of_clk_src_onecell_get() return the following: * valid clk pointers for all clocks registered; * ERR_PTR(-EINVAL) if (idx >= clk_data->clk_num); * ERR_PTR(-ENOENT) if the clock at the selected index was not initialized in the device tree (and was not registered). Changes in V2: * removed brackets from the one-line for loop Signed-off-by:
Valentine Barshak <valentine.barshak@cogentembedded.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by:
Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:
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Valentine Barshak authored
Use clkidx when registering MSTP clocks instead of loop counter since the value is then used to access the specific clock index bit in the mstp register. The issue was introduced by the following commit: f94859c2 "clk: shmobile: Add MSTP clock support" Changes in V2: * none Signed-off-by:
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- 09 Jan, 2014 1 commit
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Mike Turquette authored
Merge tag 'for_3.14/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung (A bit late) first round of Samsung clock patches for v3.14.
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- 08 Jan, 2014 14 commits
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Tomasz Figa authored
This patch adds a label and #clock-cells property to device node of max77686 PMIC to allow using it as a clock provider. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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Tomasz Figa authored
If max77686 chip is instantiated from device tree, it is desirable to have an OF clock provider to allow device tree based look-up of clocks. This patch adds OF clock provider registration to the clk-max77686 driver. Signed-off-by:
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Tomasz Figa authored
As a prerequisite for further patch adding OF clock provider support to the driver, this patch changes the driver to store an array of struct clk * as driver data. Signed-off-by:
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Tomasz Figa authored
This patch fixes invalid kfree() and adds missing call to clk_unregister() in error and remove paths in max77686_clk_probe(). While at it, error handling is also cleaned up. Signed-off-by:
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Tomasz Figa authored
As a preparation for further patches, this patch modifies the clock registration helper function to return a pointer to the newly registered clock. No functional change is done to the driver. Signed-off-by:
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Tomasz Figa authored
The function can simply return 0, without jumping to a separate label, which does exactly the same. This patch does not introduce any functional change, just a clean-up. Signed-off-by:
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Tomasz Figa authored
It is usually nice to know frequency of a clock, so this patch adds a .recalc_rate() callback returning rates of provided clocks. Signed-off-by:
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Tomasz Figa authored
Changing status of clock gates in max77686 requires i2c transfers, which can sleep, so this is done in prepare and unprepare callbacks. Due to this, checking whether whether the clock is ungated must be done in is_prepared() callback as well, for consistency. Signed-off-by:
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Tomasz Figa authored
This patch adds an entry for Samsung SoC clock drivers located under drivers/clk/samsung/ directory, with me taking the maintainer role. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Acked-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by:
Kukjin Kim <kgene.kim@samsung.com> Acked-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
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Andrew Bresticker authored
Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in) for the AudioSS clock controller. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Acked-by:
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Andrew Bresticker authored
The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by:
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Andrew Bresticker authored
Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS clock controller. Signed-off-by:
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Andrew Bresticker authored
There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by:
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Andrew Bresticker authored
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by:
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