- 30 Aug, 2024 13 commits
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Claudiu Beznea authored
Document the RZ/G3S PHY bindings. The RZ/G3S USB PHY is almost identical with the RZ/G2L USB PHY. The difference is that there is a hardware limitation on the max burst size used when the BUS master interface issues a transfer request for RZ/G3S that is configured though PHY registers. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240822152801.602318-12-claudiu.beznea.uj@bp.renesas.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Claudiu Beznea authored
The Renesas RZ/G3S need to initialize the USB BUS before transferring data due to hardware limitation. As the register that need to be touched for this is in the address space of the USB PHY, and the UBS PHY need to be initialized before any other USB drivers handling data transfer, add support to initialize the USB BUS. As the USB PHY is probed before any other USB drivers that enables clocks and de-assert the reset signals and the BUS initialization is done in the probe phase, we need to add code to de-assert reset signal and runtime resume the device (which enables its clocks) before accessing the registers. As the reset signals are not required by the USB PHY driver for the other USB PHY hardware variants, the reset signals and runtime PM was handled only in the function that initialize the USB BUS. The PHY initialization was done right after runtime PM enable to have all in place when the PHYs are registered. Signed-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826-phy-of-node-scope-v1-11-5b4d82582644@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Drop OF node reference immediately after using it in syscon_node_to_regmap(), which is both simpler and typical/expected code pattern. Signed-off-by:
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Krzysztof Kozlowski authored
Use dev_err_probe() to avoid dmesg flood on actual defer. This makes the code also simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Obtain the device node reference with scoped/cleanup.h to reduce error handling and make the code a bit simpler. Unlike in other typical of_node_get+syscon_node_to_regmap cases, the reference cannot be dropped immediately after syscon_node_to_regmap(), because further part of probe() uses it. Signed-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_available_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240826-phy-of-node-scope-v1-7-5b4d82582644@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_available_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_available_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20240826-phy-of-node-scope-v1-2-5b4d82582644@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Use scoped for_each_available_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by:
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- 29 Aug, 2024 7 commits
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Hui-Ping Chen authored
Nuvoton MA35 SoCs support DWC2 USB controller. Add the driver to drive the USB 2.0 PHY transceivers. Signed-off-by:
Hui-Ping Chen <hpchen0nvt@gmail.com> Link: https://lore.kernel.org/r/20240805030356.14565-3-hpchen0nvt@gmail.comSigned-off-by:
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Hui-Ping Chen authored
Add dt-bindings for USB2 PHY found on the Nuvoton MA35 SoC. Signed-off-by:
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Qiang Yu authored
Currently, only the RX and TX tables are written to the second PHY (port B) when the 4-lanes mode is configured, but according to Qualcomm internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need to be written as well. Signed-off-by:
Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.orgSigned-off-by:
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Lorenzo Bianconi authored
Align phy-pcie initialization delay to the vendor sdk in airoha_pcie_phy_init routine and allow the hw to complete required configuration before proceeding Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/8af6f27857619f1e0dd227f08b8584ae8fb22fb2.1722959625.git.lorenzo@kernel.orgSigned-off-by:
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Krzysztof Kozlowski authored
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Signed-off-by:
Rob Herring (Arm) <robh@kernel.org> Reviewed-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20240818172835.121757-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Abel Vesa authored
The sixth PCIe controller on X1E80100 can be used in either 4-lanes mode or 2-lanes mode. Add the configuration and compatible for the 4-lane mode. Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Abel Vesa authored
The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or 2-lane mode. Document the 4-lane mode as a separate compatible. Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
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- 05 Aug, 2024 5 commits
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Cristian Ciocaltea authored
The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC CRU. It provides more accurate clock rates required by VOP2 to improve existing support for display modes handling, which is known to be problematic when dealing with non-integer refresh rates, among others. It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-4-6a2d2164e508@collabora.comSigned-off-by:
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Cristian Ciocaltea authored
The HDMI PHY can be used as a clock provider on RK3588 SoC, hence add the necessary '#clock-cells' property. Acked-by:
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Cristian Ciocaltea authored
When a new PHY is created via [devm_]phy_create(), the runtime PM for it is not enabled unless the parent device (which creates the PHY) has its own runtime PM already enabled. Move the call to devm_pm_runtime_enable() before devm_phy_create() to enable runtime PM at PHY core level. With this change the ->power_on() and ->power_off() callbacks do not require explicit runtime PM management anymore, since the PHY core handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and phy_power_off() are invoked. Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and pm_runtime_put() helpers. Reviewed-by:Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Cristian Ciocaltea authored
Driver makes use of helpers from pm_runtime.h, but relies on the header file being implicitly included. Explicitly pull the header in to avoid potential build failures in some configurations. Fixes: 553be283 ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Reviewed-by:
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Siddharth Vadapalli authored
The Torrent SERDES can support at most two different protocols (PHY types). This only mandates that the device-tree sub-nodes used to represent the configuration should describe links with at-most two different protocols. The existing implementation however imposes an artificial constraint that allows only two links (device-tree sub-nodes). As long as at-most two protocols are chosen, using more than two links to describe them in an alternating configuration is still a valid configuration of the Torrent SERDES. A 3-Link 2-Protocol configuration of the 4-Lane SERDES can be: Lane 0 => Protocol 1 => Link 1 Lane 1 => Protocol 1 => Link 1 Lane 2 => Protocol 2 => Link 2 Lane 3 => Protocol 1 => Link 3 A 4-Link 2-Protocol configuration of the 4-Lane SERDES can be: Lane 0 => Protocol 1 => Link 1 Lane 1 => Protocol 2 => Link 2 Lane 2 => Protocol 1 => Link 3 Lane 3 => Protocol 2 => Link 4 Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240805092607.143869-1-s-vadapalli@ti.comSigned-off-by:
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- 04 Aug, 2024 2 commits
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Chen Ni authored
Replace a comma between expression statements by a semicolon. Signed-off-by:
Chen Ni <nichen@iscas.ac.cn> Link: https://lore.kernel.org/r/20240710031626.2003110-1-nichen@iscas.ac.cnSigned-off-by:
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Stefan Eichenberger authored
According to the CN9100_MPP_information document, CP_SRD4 (comphy 4) supports 2500 BASE-X and 5000 BASE-R for ETH_PORT1. I was able to test that 2500 BASE-X is indeed supported. Unfortunately, our HW does not support 5000 BASE-R, but I assume from the document that it does, so I set the muxing there too to 0x1. Signed-off-by:
Stefan Eichenberger <eichest@gmail.com> Link: https://lore.kernel.org/r/20240711131612.98952-1-eichest@gmail.comSigned-off-by:
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- 31 Jul, 2024 12 commits
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Manivannan Sadhasivam authored
These register prints are useful to validate the init sequence against the Qcom internal documentation and also to share with the Qcom hw engineers to debug issues related to PHY. Sample debug prints: qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9 qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11 Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Christophe JAILLET authored
'cdns_sierra_pll_mux_table' is not modified in this driver. And it is only used as a "const u32 *". Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 60937 3894 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o After: ===== text data bss dec hex filename 60897 3878 16 64791 fd17 drivers/phy/cadence/phy-cadence-sierra.o Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/43d881d52e3c1632ad197d4c2c18b6c481a13b24.1720723132.git.christophe.jaillet@wanadoo.frSigned-off-by:
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Christophe JAILLET authored
'struct cdns_sierra_vals' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 60521 4310 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o After: ===== text data bss dec hex filename 60937 3894 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o Signed-off-by:
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Christophe JAILLET authored
'struct cdns_reg_pairs' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 60489 4342 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o After: ===== text data bss dec hex filename 60521 4310 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o Signed-off-by:
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Christophe JAILLET authored
'cdns_torrent_refclk_driver_mux_table' is not modified in this driver. And it is only used as a "const u32 *". Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 93578 4798 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o After: ===== text data bss dec hex filename 93606 4790 16 98412 1806c drivers/phy/cadence/phy-cadence-torrent.o Signed-off-by:
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Christophe JAILLET authored
'struct cdns_torrent_vals' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 92234 6078 16 98328 18018 drivers/phy/cadence/phy-cadence-torrent.o After: ===== text data bss dec hex filename 93578 4798 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o Signed-off-by:
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Christophe JAILLET authored
'struct cdns_torrent_vals_entry' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 85130 13214 16 98360 18038 drivers/phy/cadence/phy-cadence-torrent.o After: ===== text data bss dec hex filename 92234 6078 16 98328 18018 drivers/phy/cadence/phy-cadence-torrent.o Signed-off-by:
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Christophe JAILLET authored
'struct cdns_reg_pairs' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 78154 20222 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o After: ===== text data bss dec hex filename 85130 13214 16 98360 18038 drivers/phy/cadence/phy-cadence-torrent.o Signed-off-by:
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Rayyan Ansari authored
Remove the bindings for the Qualcomm 8x16 PHY driver that was dropped in commit 4756f35f ("usb: phy: remove phy-qcom-8x16-usb.c") in 2017. Signed-off-by:
Rayyan Ansari <rayyan.ansari@linaro.org> Reviewed-by:
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Rob Herring (Arm) authored
Convert the hisilicon,hi3798cv200-combphy binding to DT schema format. Drop the example as arm/hisilicon/controller/hi3798cv200-perictrl.yaml already contains an example of this binding. Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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André Draszik authored
Use of FIELD_PREP_CONST() was a thinko - it's meant to be used for (constant) initialisers, not constant values. Use FIELD_PREP() where possible. It has better error checking and is therefore the preferred macro to use in those cases. Signed-off-by:
André Draszik <andre.draszik@linaro.org> Reviewed-by:
Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240710-phy-field-prep-v1-1-2fa3f7dc4fc7@linaro.orgSigned-off-by:
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Rayyan Ansari authored
Convert the bindings for the SATA PHY on both apq8064 and ipq806x from the old text format to yaml. Signed-off-by:
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- 28 Jul, 2024 1 commit
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Linus Torvalds authored
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