1. 06 Mar, 2011 1 commit
  2. 02 Mar, 2011 1 commit
    • Shawn Guo's avatar
      dmaengine: mxs-dma: add dma support for i.MX23/28 · a580b8c5
      Shawn Guo authored
      This patch adds dma support for Freescale MXS-based SoC i.MX23/28,
      including apbh-dma and apbx-dma.
      
      * apbh-dma and apbx-dma are supported in the driver as two mxs-dma
        instances.
      
      * apbh-dma is different between mx23 and mx28, hardware version
        register is used to differentiate.
      
      * mxs-dma supports pio function besides data transfer.  The driver
        uses dma_data_direction DMA_NONE to identify the pio mode, and
        steals sgl and sg_len to get pio words and numbers from clients.
      
      * mxs dmaengine has some very specific features, like sense function
        and the special NAND support (nand_lock, nand_wait4ready).  These
        are too specific to implemented in generic dmaengine driver.
      
      * The driver refers to imx-sdma and only a single descriptor is
        statically assigned to each channel.
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      a580b8c5
  3. 26 Feb, 2011 2 commits
    • Tomoya MORINAGA's avatar
      pch_dma: set the number of array correctly · 26d890f0
      Tomoya MORINAGA authored
      set the number of array correctly.
      Signed-off-by: default avatarTomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      26d890f0
    • Tomoya MORINAGA's avatar
      pch_dma: fix kernel error issue · c5a9f9d0
      Tomoya MORINAGA authored
      fix the following kernel error
      
      ------------[ cut here ]------------
      WARNING: at kernel/softirq.c:159 _local_bh_enable_ip.clone.5+0x35/0x71()
      Hardware name: To be filled by O.E.M.
      Modules linked in: pch_uart pch_dma fuse mga drm cpufreq_ondemand acpi_cpufreq mperf ip6t_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 ip6table_filter ip6_tables ipv6 uinput snd_hda_codec_realtek snd_hda_intel snd_hda_codec matroxfb_base snd_hwdep 8250_pnp snd_seq snd_seq_device matroxfb_DAC1064 snd_pcm joydev 8250 matroxfb_accel snd_timer matroxfb_Ti3026 ppdev pegasus parport_pc snd parport matroxfb_g450 g450_pll serial_core video output matroxfb_misc soundcore snd_page_alloc serio_raw pcspkr ext4 jbd2 crc16 sdhci_pci sdhci mmc_core floppy [last unloaded: scsi_wait_scan]
      Pid: 0, comm: swapper Not tainted 2.6.37.upstream_check+ #8
      Call Trace:
       [<c0433add>] warn_slowpath_common+0x65/0x7a
       [<c043825b>] ? _local_bh_enable_ip.clone.5+0x35/0x71
       [<c0433b01>] warn_slowpath_null+0xf/0x13
       [<c043825b>] _local_bh_enable_ip.clone.5+0x35/0x71
       [<c043829f>] local_bh_enable_ip+0x8/0xa
       [<c06ec471>] _raw_spin_unlock_bh+0x10/0x12
       [<f82b57dd>] pd_prep_slave_sg+0xba/0x200 [pch_dma]
       [<f82f7b7a>] pch_uart_interrupt+0x44d/0x6aa [pch_uart]
       [<c046fa97>] handle_IRQ_event+0x1d/0x9e
       [<c047146f>] handle_fasteoi_irq+0x90/0xc7
       [<c04713df>] ? handle_fasteoi_irq+0x0/0xc7
       <IRQ>  [<c04045af>] ? do_IRQ+0x3e/0x89
       [<c04035a9>] ? common_interrupt+0x29/0x30
       [<c04400d8>] ? sys_getpriority+0x12d/0x1a2
       [<c058bb2b>] ? arch_local_irq_enable+0x5/0xb
       [<c058c740>] ? acpi_idle_enter_bm+0x22a/0x261
       [<c0648b11>] ? cpuidle_idle_call+0x70/0xa1
       [<c0401f44>] ? cpu_idle+0x49/0x6a
       [<c06d9fc4>] ? rest_init+0x58/0x5a
       [<c089e762>] ? start_kernel+0x2d0/0x2d5
       [<c089e0ce>] ? i386_start_kernel+0xce/0xd5
      Signed-off-by: default avatarTomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      c5a9f9d0
  4. 14 Feb, 2011 4 commits
    • Dan Williams's avatar
      Merge branch 'dw_dmac' into dmaengine · 0670e715
      Dan Williams authored
      0670e715
    • Dan Williams's avatar
      Merge branch 'dma40' into dmaengine · 80cc07af
      Dan Williams authored
      80cc07af
    • Dan Williams's avatar
      Merge branch 'imx' into dmaengine-fixes · e19d1d49
      Dan Williams authored
      e19d1d49
    • Anatolij Gustschin's avatar
      dma: ipu_idmac: do not lose valid received data in the irq handler · a646bd7f
      Anatolij Gustschin authored
      Currently when two or more buffers are queued by the camera driver
      and so the double buffering is enabled in the idmac, we lose one
      frame comming from CSI since the reporting of arrival of the first
      frame is deferred by the DMAIC_7_EOF interrupt handler and reporting
      of the arrival of the last frame is not done at all. So when requesting
      N frames from the image sensor we actually receive N - 1 frames in
      user space.
      
      The reason for this behaviour is that the DMAIC_7_EOF interrupt
      handler misleadingly assumes that the CUR_BUF flag is pointing to the
      buffer used by the IDMAC. Actually it is not the case since the
      CUR_BUF flag will be flipped by the FSU when the FSU is sending the
      <TASK>_NEW_FRM_RDY signal when new frame data is delivered by the CSI.
      When sending this singal, FSU updates the DMA_CUR_BUF and the
      DMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY
      is cleared, indicating that the frame data is beeing written by
      the IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be
      set to the ready state again by the MCU, when it has handled the
      received data. DMAIC_7_CUR_BUF flag won't be flipped here by the
      IPU, so waiting for this event in the EOF interrupt handler is wrong.
      Actually there is no spurious interrupt as described in the comments,
      this is the valid DMAIC_7_EOF interrupt indicating reception of the
      frame from CSI.
      
      The patch removes code that waits for flipping of the DMAIC_7_CUR_BUF
      flag in the DMAIC_7_EOF interrupt handler. As the comment in the
      current code denotes, this waiting doesn't help anyway. As a result
      of this removal the reporting of the first arrived frame is not
      deferred to the time of arrival of the next frame and the drivers
      software flag 'ichan->active_buffer' is in sync with DMAIC_7_CUR_BUF
      flag, so the reception of all requested frames works.
      
      This has been verified on the hardware which is triggering the
      image sensor by the programmable state machine, allowing to
      obtain exact number of frames. On this hardware we do not tolerate
      losing frames.
      
      This patch also removes resetting the DMA_BUFx_RDY flags of
      all channels in ipu_disable_channel() since transfers on other
      DMA channels might be triggered by other running tasks and the
      buffers should always be ready for data sending or reception.
      Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
      Reviewed-by: default avatarGuennadi Liakhovetski <g.liakhovetski@gmx.de>
      Tested-by: default avatarGuennadi Liakhovetski <g.liakhovetski@gmx.de>
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      a646bd7f
  5. 31 Jan, 2011 32 commits