- 11 Nov, 2012 40 commits
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Daniel Vetter authored
dev_priv has grown way too big, and grouping memebers into substructs and moving them out of line helps re-gain some overview. Unfortunatley I couldn't just call the substruct save and drop the prefix, since that will make most member names clash with registers #defines. Changes in i915_drv.h done by hand, everything else changed with s/\<save\([A-Z]*\)/regfile.save\1/ in vim. Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Jesse Barnes authored
So we can write them properly. Signed-off-by:
Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by:
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Jesse Barnes authored
"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by:
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Jesse Barnes authored
So store into the scratch space of the HWS to make sure the invalidate occurs. v2: use GTT address space for store, clean up #defines (Chris) v3: use correct #define in blt ring flush (Chris) Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252Signed-off-by:
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Jesse Barnes authored
Workaround for dual port PS dispatch on GT1. v2: pull in register definition & offset handling v3: use IVB GT1 macro to get the right regs (Ben) v4: add for VLV too (Ben) v5: don't read the reg, it's masked so we'll only enable the one extra bit (Chris) v6: use a _GT2 suffix for the second reg (Chris) Signed-off-by:
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Jesse Barnes authored
This allows us to get the right vblank interrupt frequency. v2: pull in register definition Signed-off-by:
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Jesse Barnes authored
References: https://bugs.freedesktop.org/show_bug.cgi?id=50250Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Jesse Barnes authored
v2: use correct register v3: remove extra hunks, pull in register definitions & offset check directly v4: add GT1 vs GT2 distinction for IVB portion (Ben) References: https://bugs.freedesktop.org/show_bug.cgi?id=50233Reviewed-by:
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Jesse Barnes authored
Needs to be set on every context restore as well, so set it as part of the initial state so we can save/restore it. Note this removes the IVB workaround value from VLV and uses the default value, just adding in the L3 cache aging disable bit, since the IVB value is wrong for VLV. Signed-off-by:
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Paulo Zanoni authored
This covers the "Disable FDI" section from the CRT mode set sequence. This disables the FDI receiver and also the FDI pll. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Paulo Zanoni authored
This commit makes hsw_fdi_link_train responsible for implementing everything described in the "Enable and train FDI" section from the Hawell CRT mode set sequence documentation. We completely rewrite hsw_fdi_link_train to match the documentation and we also call it in the right place. This patch was initially sent as a series of tiny patches fixing every little problem of the function, but since there were too many patches fixing the same function it got a little difficult to get the "big picture" of how the function would be in the end, so here we amended all the patches into a single big patch fixing the whole function. Problems we fixed: 1 - Train Haswell FDI at the right time. We need to train the FDI before enabling the pipes and planes, so we're moving the call from lpt_pch_enable to haswell_crtc_enable directly. We are also removing ironlake_fdi_pll_enable since the PLL enablement on Haswell is completely different and is also done during the link training steps. 2 - Use the right FDI_RX_CTL register on Haswell There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using "pipe" here is wrong. 3 - Don't rely on DDI_BUF_CTL previous values Just set the bits we want, everything else is zero. Also POSTING_READ the register before sleeping. 4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train According to the mode set sequence documentation, this is the right place. According to the FDI_RX_TUSIZE register description, this is the value we should set. Also remove the code that sets this register from the old location: lpt_pch_enable. 5 - Properly program FDI_RX_MISC pwrdn lane values on HSW 6 - Wait only 35us for the FDI link training First we wait 30us for the FDI receiver lane calibration, then we wait 5us for the FDI auto training time. 7 - Remove an useless indentation level on hsw_fdi_link_train We already "break" when the link training succeeds. 8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE When we fail the training. 9 - Change Haswell FDI link training error messages We shouldn't call DRM_ERROR when still looping through voltage levels since this is expected and not really a failure. So in this commit we adjust the error path to only DRM_ERROR when we really fail after trying everything. While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since it's what we use everywhere. 10 - Try each voltage twice at hsw_fdi_link_train Now with Daniel Vetter's suggestion to use "/2" instead of ">>1". Signed-off-by: -
Jani Nikula authored
Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Paulo Zanoni authored
We had 2 places using X2 and one place using X1. Signed-off-by:
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Daniel Vetter authored
Now that we no longer pretend to have flexibility in matching any north display block with any pch, we can ditch this. v2: Fix the embarassing rebase fail that Paulo Zanoni spotted. Reviewed-by:
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Daniel Vetter authored
Found in Bspec vol4h South Display Engine Registers [CPT, PPT], section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1" v2: Make it compile. Reviewed-by:
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Daniel Vetter authored
We need to set the timing override chicken bit after fdi link training has completed and before we enable the transcoder. We also have to clear that bit again after disabling the pch transcoder. See "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31: "Workaround : Enable the override prior to enabling the transcoder. Disable the override after disabling the transcoder." While at it, use the _PIPE macro for the other TRANS_DP register. v2: Keep the w/a as-is, but kill the original (but wrongly placed) workaround introduced in commit 3bcf603f Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Jul 27 11:51:40 2011 -0700 drm/i915: apply timing generator bug workaround on CPT and PPT and commit d4270e57 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Tue Oct 11 10:43:02 2011 -0700 drm/i915: export a CPT mode set verification function Note that this old code has unconditionally set the w/a, which might explain why fdi link training sometimes silently fails, and especially why the auto-train did not seem to work properly. v3: Paulo Zanoni pointed out that this workaround is also required on the LPT PCH. And Arthur Ranyan confirmed that this workaround is requierd for all ports on the pch, not just DP: The important part is that the bit is set whenever the pch transcoder is enabled, and that it is _not_ set while the fdi link is trained. It is also important that the pch transcoder is fully disabled, i.e. we have to wait for bit 30 to clear before clearing the w/a bit. Hence move to workaround into enable/disable_transcoder, where the pch transcoder gets enabled/disabled. v4: Whitespace changes dropped. v5: Don't run the w/a on IBX, we only need it on CPT/PPT and LPT. v6: - resolve conflicts with Paulo's big hsw vga rework - s/!IBX/CPT since hsw paths are now all separate, and Paulo's patch to implement the equivalent w/a for LPT is already merged. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Paulo Zanoni <przanoni@gmail.com> Cc: Arthur Ranyan <arthur.j.runyan@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v5) Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v5) Signed-off-by:
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Daniel Vetter authored
They are all written for a specific north disaplay->pch combination. So stop pretending otherwise. Reviewed-by:
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Daniel Vetter authored
We don't really support fancy north display/pch combinations, so put a big yelling WARN_ON in there. It /should/ be impossible, but alas, the rumours don't stop (mostly due to really early silicon sometimes using older PCHs). v2: Fixup the logic fumble noticed by Paulo Zanoni. I should actually try to test run the patch next time around ... Reviewed-by:
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Daniel Vetter authored
This essentially reverts commit cb0953d7 Author: Adam Jackson <ajax@redhat.com> Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else simply because it doesn't scale: It misses SDVO and DVO panels, and now with DDI encoders on haswell this is becoming unmanageable. Instead we simply sort the connector list after everything is set up. Reviewed-by:
Adam Jackson <ajax@redhat.com> Acked-by:
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Daniel Vetter authored
Userspace seems to like this, see commit cb0953d7 Author: Adam Jackson <ajax@redhat.com> Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else This makes them sort to the front in X, which makes them likely to be the primary outputs if you haven't specified a preference in your DE, which is likely to be what you want. Signed-off-by:
Eric Anholt <eric@anholt.net> Sorting the connector list after the fact is much easier than trying to be clever with the init sequence. Acked-by:
Dave Airlie <airlied@gmail.com> Reviewed-by:
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Paulo Zanoni authored
On Haswell/LPT we must disable the PCH transcoder before we disable the FDI, so don't check for disabled FDI there. Signed-off-by:
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Paulo Zanoni authored
This function is only for the previous gens. Signed-off-by:
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Paulo Zanoni authored
These workarounds are documented on the CRT mode set sequence. Signed-off-by:
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Paulo Zanoni authored
... instead of "pipe", which is wrong. Signed-off-by:
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Ville Syrjälä authored
Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Paulo Zanoni authored
... instead of PIPECONF_INTERLACE_MASK. Signed-off-by:
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Paulo Zanoni authored
That function is made for IBX. Running it on LPT will trigger tons of "unclaimed register" errors. The only port remaining on LPT is PCH_ADPA. Signed-off-by:
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Paulo Zanoni authored
Because we already set all the bits we can set. Signed-off-by:
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Paulo Zanoni authored
... instead of using "pipe". As already explained in previous commits, since Haswell/LPT cpu_transcoder, pch_transcoder and pipe are not the same thing. Signed-off-by:
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Paulo Zanoni authored
These asserts are specific to IBX/CPT/PPT. Inside the assert_pch_pll function we even "return" in case we detect LPT, but I prefer to just not call it. In the future we might rename to something like ibx_assert_pch_pll. Signed-off-by:
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Paulo Zanoni authored
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Paulo Zanoni authored
Since now we have lpt_enable_pch_transcoder. Signed-off-by:
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Paulo Zanoni authored
For now the new functions are just copies. Differences will be added later. Signed-off-by:
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Paulo Zanoni authored
To ironlake_{en,dis}able_pch_transcoder since these functions will be different on Haswell/LPT and since the "transcoder" they {en,dis}able is on the PCH. Signed-off-by: -
Paulo Zanoni authored
On Haswell/LPT, pipe, cpu_transcoder and pch_transcoder are different things with different values, unlinke the previous gens. So here we use the right thing at the right place. Signed-off-by:
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Paulo Zanoni authored
There is no LVDS, so don't poke the LVDS registers. Signed-off-by:
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Paulo Zanoni authored
This is just wrong. The lpt_program_iclkip should disable the PCH pixel clocks (and yes, we plan to rename it later). Signed-off-by:
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Paulo Zanoni authored
Because this function is only for the older PCHs, not the newer ones. Signed-off-by:
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Paulo Zanoni authored
Since this function will only run on Haswell/LPT and newer. Signed-off-by:
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Paulo Zanoni authored
Since now we have lpt_pch_enable for them. Signed-off-by:
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