- 06 Apr, 2017 34 commits
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Alex Xie authored
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Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Xie authored
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Monk Liu authored
Implement the sr-iov mailbox for soc15 asics. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
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Monk Liu authored
they are lack in the bringup stage, we need them for GPU reset feature. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
1,KIQ won't touch VRAM so no need to involv HDP flush/invalidate at all. 2,According to CP hw designer KIQ better not use any PM4 package lead to wait behave. Signed-off-by:
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Monk Liu authored
SRIOV currently only can load ucode directly, and PSP block is not supported by VF temporarily. will remove this restrict and use PSP load all ucode even for SRIOV later v2: squash in check against module parameter Signed-off-by:
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Evan Quan authored
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Evan Quan <evan.quan@amd.com> Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
Use new WREG32_FIELD macro Signed-off-by:
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Tom St Denis authored
It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by:
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Alex Xie authored
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Christian König authored
We need an array of pointers to IRQ sources, not an array of sources. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
Had the wrong sense in the loop Signed-off-by:
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Christian König authored
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by:
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Zhang, Jerry authored
Set reasonable defaults per family. v2: set both of them in gmc v3: move vm size and block size in vm manager v4: squash in warning fix from Alex Xie v5: squash in min() warning fix Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
Clean up a toggle with ?:. Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
Swap read/write pattern for WREG32_FIELD() Signed-off-by:
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Tom St Denis authored
Swap read/write pattern for WREG32_FIELD() Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by:
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Alex Deucher authored
Set the ready flag to reflect this. Reviewed-by:
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Christian König authored
The two hubs are just instances of the same hardware, so the register bits are identical. v2: only remove get_vm_protection_bits for now Signed-off-by:
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Christian König authored
This avoids merging them together on page fault. v2: squash in 64-bit division fix Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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- 05 Apr, 2017 6 commits
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Christian König authored
Implement AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS using TTM_PL_FLAG_CONTIGUOUS instead of a placement limit. That allows us to better handle CPU accessible placements. v2: prevent virtual BO start address from overflowing Signed-off-by:
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Christian König authored
We should probably rename amdgpu_gart_funcs sooner or later. Reviewed-by:
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Christian König authored
Remove some of the extra checks where they don't hurt us. Reviewed-by:
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Christian König authored
Abort early if there is nothing todo and correctly indent the "if"s. Reviewed-by:
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Christian König authored
The name is a bit confusing and the extra "? true : false" is superflous. Additional to that remove setting the reset counter directly after checking it. Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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