- 24 Nov, 2020 40 commits
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:115: warning: Function parameter or member 'adev' not described in 'amdgpu_virt_request_full_gpu' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:115: warning: Excess function parameter 'amdgpu' description in 'amdgpu_virt_request_full_gpu' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:138: warning: Function parameter or member 'adev' not described in 'amdgpu_virt_release_full_gpu' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:138: warning: Excess function parameter 'amdgpu' description in 'amdgpu_virt_release_full_gpu' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:159: warning: Function parameter or member 'adev' not described in 'amdgpu_virt_reset_gpu' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:159: warning: Excess function parameter 'amdgpu' description in 'amdgpu_virt_reset_gpu' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:194: warning: Function parameter or member 'adev' not described in 'amdgpu_virt_wait_reset' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:194: warning: Excess function parameter 'amdgpu' description in 'amdgpu_virt_wait_reset' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:210: warning: Function parameter or member 'adev' not described in 'amdgpu_virt_alloc_mm_table' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:210: warning: Excess function parameter 'amdgpu' description in 'amdgpu_virt_alloc_mm_table' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:239: warning: Function parameter or member 'adev' not described in 'amdgpu_virt_free_mm_table' drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:239: warning: Excess function parameter 'amdgpu' description in 'amdgpu_virt_free_mm_table' Acked-by:
Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/cik_ih.c:189: warning: Function parameter or member 'ih' not described in 'cik_ih_get_wptr' drivers/gpu/drm/amd/amdgpu/cik_ih.c:274: warning: Function parameter or member 'ih' not described in 'cik_ih_set_rptr' Acked-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:127: warning: Function parameter or member 'job' not described in 'amdgpu_ib_schedule' Acked-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1214: warning: Function parameter or member 'page_flags' not described in 'amdgpu_ttm_tt_create' Acked-by:
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/radeon/radeon_device.c:637:6: warning: no previous prototype for ‘radeon_device_is_virtual’ [-Wmissing-prototypes] Acked-by:
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Simon Ser authored
Setting any rotation on the cursor plane is ignored by amdgpu. Because of DCE/DCN design, it's not possible to rotate the cursor. Instead of displaying the wrong result, stop advertising the rotation property for the cursor plane. Now that we check all cursor plane properties in amdgpu_dm_atomic_check, remove the TODO. Reviewed-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Simon Ser authored
Don't allow user-space to set different scaling parameters for the cursor plane and for the primary plane. Because of DCE/DCN design, it's not possible to have a mismatch. The old check in dm_update_plane_state is superseded by this new check. Reviewed-by:
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Simon Ser authored
Looking at handle_cursor_update, it doesn't seem like src_{x,y,w,h} are picked up by DC. I also tried to change these parameters via a test KMS client, and amdgpu ignored them. Instead of displaying the wrong result, reject the atomic commit. Reviewed-by: -
Simon Ser authored
This patch expands the cursor checks added in "drm/amd/display: add basic atomic check for cursor plane" to also include a FB size check. Without this patch, setting a FB smaller than max_cursor_size with an invalid width would result in amdgpu error messages and a fallback to a 64-byte width: [drm:hubp1_cursor_set_attributes [amdgpu]] *ERROR* Invalid cursor pitch of 100. Only 64/128/256 is supported on DCN. Note that DC uses the word "pitch" when actually checking the FB width. Indeed, the function handle_cursor_update does this: attributes.pitch = attributes.width; In my tests, the cursor FB actually had a pitch of 512 bytes. Reviewed-by:Pierre-Loup A. Griffais <pgriffais@valvesoftware.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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shaoyunl authored
This function actually control the vblank on/off. It shouldn't be bypassed for VF. Otherwise all the vblank based feature on VF will not work. Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Yongqiang Sun authored
[Why & How] Update init soc bounding box and bw bounding box for DCN3.01. Remove pp smu interface which isn't used. v2: squash in removal of stable function definition (Alex) Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Camille Cho authored
[Why] Cached backlight is never being updated since panel_cntl specific registers were moved from abm to panel_cntl. [How] Update cached backlight in set_abm_immediate_disable as what we used to do. Also, update the priority of backlight restore mechanism so that cached backlight has the highest priority since it is always correct. Signed-off-by:
Camille Cho <Camille.Cho@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Sung Joon Kim authored
[why] ASIC requirement. [how] Make disable_*_power_gate to false. Signed-off-by:
Sung Joon Kim <sungjoon.kim@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Jacky Liao authored
[Why] The GAMCOR memory blocks should be powered down when they're not in use. This will reduce power consumption. [How] Write to GAMCOR_MEM_PWR_FORCE to put memory to shutdown when GAMCOR is not used. Signed-off-by:
Jacky Liao <ziyu.liao@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] Remove temp macro since the enum is in header file already. Signed-off-by:
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Yongqiang Sun authored
[Why & How] only apply multiple display power optimization in case there are more than one internal display. Signed-off-by:
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Yongqiang Sun authored
[Why & How] Get internal display info from vbios and pass it to dmub fw to determine if multiple display optmization is needed. Signed-off-by:
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Jacky Liao authored
[Why] The BLNDGAM memory blocks should be powered down when they're not in use. This will reduce power consumption. [How] 1. Write to BLNDGAM_MEM_PWR_FORCE to put memory to shutdown when BLNDGAM is not used. 2. Added a debug option to allow this behaviour to be turned off Signed-off-by:
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Wyatt Wood authored
[Why] Need to clear sticky error bits generated during hpd irq from receiver. [How] Clear sticky vsc sdp error bit. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Sherry authored
[Why] t9 delay func is called twice after setting power off, the unexpected action results in a doubling of the added 140ms t9 delay [How] If the backlight has been turned off, does not turn it off again Signed-off-by:
Sherry <Yao.Wang1@amd.com> Reviewed-by:
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Eric Yang authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Tashfique Abdullah authored
[Why] The MPCC may change and request data when the pipes are switching from 2 to 1 or 1 to 2. During the switch there is a possibility of underflow and flicker/missing data. [How] During VBlank the MPCC won't request data. The trick is to delay and wait on VBlank, ONLY when pipes are either turning on or off, right before MPCC is reset for the pipes. Signed-off-by:
Tashfique Abdullah <tabdullah@amd.com> Reviewed-by:
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Jacky Liao authored
[Why] On some platforms, DMCU is no longer used. In these cases, some DMCU memory should be completely powered off to save power. [How] 1. Set DMCU_ERAM_MEM_PWR_FORCE to shutdown memory when DMCU is not in use 2. Added a debug option to allow this behaviour to be turned off 3. Set all memory low power debug options to off first, to not immediately cause problems Signed-off-by:
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Yongqiang Sun authored
[Why & How] Enable stutter for DCN3.01. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Chris Park authored
[Why] Incorrect panel register settings are applied for power sequence because the register macro is not defined in resource. [How] Implement same register space to future resource files. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Ashley Thomas authored
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Charlene Liu authored
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] slower down the HW i2c speed when used by HW i2c. this request: each acquired_i2c_engine setup the i2c speed needed. and set the I2c engine for HDCP use at release_engine. this covers SW using HW I2c engine and HDCP using HW I2c engine. for dmcu using HW I2c engine, needs add similar logic in dmcufw. Signed-off-by:
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Christian König authored
Same as gmc9, basically filter the fault, reroute or handle it. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Felix pointed out that we need this for Navi as well. Signed-off-by:
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Christian König authored
Looks like we can't enabled the IH1/IH2 feature for Vega20, make sure retry faults are handled on a separate ring anyway. Signed-off-by:
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Christian König authored
Seems like we won't get the hardware IH1/2 rings on Vega20 working. Signed-off-by:
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Christian König authored
Add a soft IH ring implementation similar to the hardware IH1/2. This can be used if the hardware delegation of interrupts to IH1/2 doesn't work for some reason. Signed-off-by:
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Christian König authored
Return early in case of a ratelimit and don't print leading zeros for the address. Signed-off-by:
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Christian König authored
The address space is only 48bit, not 64bit. And the VMHUBs work with sign extended addresses. Signed-off-by:
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Nirmoy Das authored
Use generic DMA api instead of bus-specific API. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Nirmoy Das authored
Use generic DMA api instead of bus-specific API. Signed-off-by:
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Jiansong Chen authored
Update GC golden setting for navy_flounder. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Gustavo A. R. Silva authored
In preparation to enable -Wimplicit-fallthrough for Clang, fix a couple of warnings by explicitly adding a break statement instead of letting the code fall through to the next case, and a fallthrough pseudo-keyword as a replacement for a /* fall through */ comment, Notice that Clang doesn't recognize /* fall through */ comments as implicit fall-through markings. Link: https://github.com/KSPP/linux/issues/115Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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