- 20 Dec, 2019 3 commits
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Sibi Sankar authored
Add scm, smem, smp2p, aoss-qmp, aoss-cc and pdc-global device nodes to SC7180 SoCs. Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191218143332.29107-1-sibis@codeaurora.org [bjorn: Updated subject] Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Sibi Sankar authored
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs. Signed-off-by:
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Sai Prakash Ranjan authored
Update the compatible for QCS404 watchdog timer with proper SoC specific compatible. Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/757995875cc12d3f5a8f5fd5659b04653950970a.1576211720.git.saiprakash.ranjan@codeaurora.orgSigned-off-by:
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- 18 Dec, 2019 6 commits
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Douglas Anderson authored
Commit f4a73f5e ("pinctrl: qcom: sc7180: Add new qup functions") has landed which means that we absolutely need to use the proper names for the pinmuxing for I2C/UART numbers 2, 4, 7, and 9. Let's do it. For reference: - If you get only one of this commit and the pinctrl commit then none of I2C/UART 2, 4, 7, and 9 will work. - If you get neither of these commits then I2C 2, 4, 7, and 9 will work but not UART. ...but despite the above it should be fine for this commit to land in the Qualcomm tree because sc7180.dtsi only exists there (it hasn't made it to mainline). Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Rajendra Nayak <rnayak@codeaurora.org> Fixes: ba3fc649 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191217130352.1.Id8562de45e8441cac34699047e25e7424281e9d4@changeidSigned-off-by:
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Jeffrey Hugo authored
The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU. This should be hooked up to the GPU CPR, but we don't have support for that yet, so until then, just turn on the regulator and keep it on so that we can focus on basic GPU bringup. Signed-off-by:
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191217170249.5280-1-jeffrey.l.hugo@gmail.comSigned-off-by:
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Maulik Shah authored
Specify wakeup parent irqchip for sc7180 TLMM. Reviewed-by:
Lina Iyer <ilina@codeaurora.org> Reviewed-by:
Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1572419178-5750-3-git-send-email-mkshah@codeaurora.orgSigned-off-by:
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Sibi Sankar authored
Add ADSP, CDSP, MPSS and SLPI device tree nodes for SM8150 SoC. Tested-by:
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Matthias Kaehlcke authored
The SC7180 device tree nodes should be ordered by address. Re-shuffle some nodes which currently don't follow this convention. Since we are already moving it add a missing leading zero to the address in the 'reg' property of the 'interrupt-controller@b220000' node. Signed-off-by:
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Jeffrey Hugo authored
It turns out that the wcn3990 can float the gpio lines during bootup, etc which will result in the uart core thinking there is incoming data. This results in the bluetooth stack getting garbage. By applying a bias to match what wcn3990 would drive, the issue is corrected. Signed-off-by:
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- 17 Dec, 2019 1 commit
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Stephen Boyd authored
Add the cr50 device to the spi controller it is attached to. This enables /dev/tpm0 and some login things on Cheza. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20191216234204.190769-1-swboyd@chromium.orgSigned-off-by:
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- 16 Dec, 2019 1 commit
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Sibi Sankar authored
Add the SMP2P nodes for the remoteproc states for ADSP, CDSP, MPSS and SLPI remoteprocs. Signed-off-by:
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- 12 Dec, 2019 10 commits
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Douglas Anderson authored
The bindings for the QMP PHY are truly strange. I believe (?) that they may have originated because with PCIe each lane is treated as a different PHY and the same PHY driver is used for a whole bunch of things (incluidng PCIe). In any case, now that we have "make dtbs_check", we find that having the outer node named "phy" triggers the "schemas/phy/phy-provider.yaml" schema, yelling about: phy@88e9000: '#phy-cells' is a required property Let's call the outer node the "phy-wrapper" and the inner node the "phy" to make dtbs_check happy. Reviewed-by:
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Douglas Anderson authored
This is just like commit e77cc85e ("arm64: dts: qcom: sdm845: remove macro from unit name"). It fixes the error in 'make dtbs_check': arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: adc@3100: 'adc-chan@0x06' does not match any of the regexes: ... Reviewed-by:
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Douglas Anderson authored
Running "dtbs_check" yells: '#clock-cells' is a dependency of 'clock-output-names' ...and sure enough the bindings say we should have "#clock-cells". Add it. Reviewed-by:
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Douglas Anderson authored
Running `make dtbs_check` yells: arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: interrupt-controller@17a00000: gic-its@17a40000: False schema From "arm,gic-v3.yaml" we can grok that this is explained by the comment "msi-controller is preferred". Switch to the preferred name so that dtbs_check stops yelling. Reviewed-by:
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Douglas Anderson authored
Running `make dtbs_check` yells because qcom.yaml says that we should have: - items: - enum: - qcom,sc7180-idp - const: qcom,sc7180 ...but we're missing "qcom,sc7180". Add it. Reviewed-by: -
Sibi Sankar authored
Add the DT node for the rpmhpd power controller. Reviewed-by:
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Rajendra Nayak authored
Add aliases for all i2c and spi nodes Reviewed-by:
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Rajendra Nayak authored
remove the additional CS muxes that were added by default for spi so every board using sc7180 does not have to override it. Reviewed-by:
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Loic Poulain authored
The Dragonboard-410c is able to act either as USB Host or Device. The role can be determined at runtime via the USB_HS_ID pin which is derived from the micro-usb port VBUS pin. In Host role, SoC USB D+/D- are routed to the onboard USB 2.0 HUB. In Device role, SoC USB D+/D- are routed to the USB 2.0 micro B port. Routing is selected via USB_SW_SEL_PM gpio. In device role USB HUB can be held in reset. chipidea driver expects two extcon device pointers, one for the EXTCON_USB event and one for the EXTCON_USB_HOST event. Since the extcon-usb-gpio device is capable of generating both these events, point two times to this extcon device. Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1576083014-5842-1-git-send-email-loic.poulain@linaro.orgSigned-off-by:
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Stephan Gerhold authored
PM8916 has one vibration motor driver that is already supported by the pm8xxx-vibrator driver. Add a node describing it to pm8916.dtsi. Keep it disabled by default since not all devices make use of it. Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191211192906.56638-1-stephan@gerhold.netSigned-off-by:
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- 11 Dec, 2019 15 commits
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Sandeep Maheswaram authored
Add nodes for DWC3 USB controller, QMP and QUSB PHYs. Signed-off-by:
Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by:
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Rajeshwari authored
Add TSENS node and user thermal zone for TSENS sensors in SC7180. Signed-off-by:
Rajeshwari <rkambl@codeaurora.org> Link: https://lore.kernel.org/r/1574934847-30372-2-git-send-email-rkambl@codeaurora.orgSigned-off-by:
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Jeffrey Hugo authored
Add MSM8998 GPU Clock Controller DT node. Signed-off-by:
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Vinod Koul authored
Enable the UFS HC and phy nodes and add regulators used by these. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20191106084656.1749954-2-vkoul@kernel.orgSigned-off-by:
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Vinod Koul authored
Add the ufs hc node and ufs phy nodes found in SM8150 Signed-off-by:
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Vinod Koul authored
Now that header defining gcc clocks is upstream, use the enums instead of numbers Signed-off-by:
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Taniya Das authored
cpufreq hw node required to scale CPU frequency on sc7180. Reviewed-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/0101016ed02b6356-5165eaaa-6c54-47ff-a008-821c91831e56-000000@us-west-2.amazonses.comSigned-off-by:
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Manu Gautam authored
QUSB2 PHY on msm8996 doesn't work well when autosuspend by dwc3 core using USB2PHYCFG register is enabled. One of the issue seen is that PHY driver reports PLL lock failure and fails phy_init() if dwc3 core has USB2 PHY suspend enabled. Fix this by using quirks to disable USB2 PHY LPM/suspend and dwc3 core already takes care of explicitly suspending PHY during suspend if quirks are specified. Signed-off-by:
Manu Gautam <mgautam@codeaurora.org> Signed-off-by:
Paolo Pisati <p.pisati@gmail.com> Link: https://lore.kernel.org/r/20191209151501.26993-1-p.pisati@gmail.comSigned-off-by:
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Sai Prakash Ranjan authored
Add device tree node for LLCC aka system cache controller for SC7180 SoC. Signed-off-by:
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Sai Prakash Ranjan authored
Add APSS (Application Processor Subsystem) watchdog DT node for SM8150 SoC. Signed-off-by:
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Sai Prakash Ranjan authored
Add APSS (Application Processor Subsystem) watchdog DT node for SC7180 SoC. Signed-off-by:
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Sai Prakash Ranjan authored
LLCC cache-controller was renamed to system-cache-controller to make schema pass the dt binding check. Update the device tree node to reflect this change. Reviewed-by:
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Douglas Anderson authored
Make i2c7 symmetric with the other i2c busses and comment that we have no internal pull because there is an external one. Reviewed-by:
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Douglas Anderson authored
The qspi pinctrl nodes had the wrong indentation and sort ordering and the main qspi node was placed down in the pinctrl section. Fix. Reviewed-by:
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Amit Kucheria authored
Register upper-lower interrupt for the tsens controller. Signed-off-by:
Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/88eff964b708c8aff57b24370d2e14389ace09e9.1572526427.git.amit.kucheria@linaro.orgSigned-off-by:
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- 10 Dec, 2019 4 commits
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Lina Iyer authored
PDC always-on interrupt controller can detect certain GPIOs even when the TLMM interrupt controller is powered off. Link the PDC as TLMM's wakeup parent. Signed-off-by:
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Lina Iyer authored
Add PDC interrupt controller device bindings for SDM845. Signed-off-by:
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Jeffrey Hugo authored
The tcsr syscon region is really 0x40000 in size. We need access to the full region so that we can access the axi resets when managing the modem subsystem. Fixes: c7833949 ("arm64: dts: qcom: msm8998: Add smem related nodes") Signed-off-by:
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Jeffrey Hugo authored
Add the wifi node and required reserved memory to enable the wlan hardware. Enable the wifi node in both the mtp and clamshell platforms after adding the relevant regulators for each platform. Signed-off-by:
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