- 12 Jan, 2022 3 commits
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Stephen Boyd authored
* clk-nvidia: clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114 * clk-imx: clk: imx8mp: Fix the parent clk of the audio_root_clk clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h clk: imx8mn: Fix imx8mn_clko1_sels clk: imx: Use div64_ul instead of do_div clk: imx: imx8ulp: set suppress_bind_attrs to true * clk-samsung: clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks clk: samsung: exynos850: Register clocks early clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: samsung: Update CPU clk registration clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks * clk-qcom: (25 commits) clk: qcom: gcc-sc7280: Mark gcc_cfg_noc_lpass_clk always enabled clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock ...
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Stephen Boyd authored
* clk-x86: clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: Introduce clk-tps68470 driver platform/x86: int3472: Deal with probe ordering issues platform/x86: int3472: Pass tps68470_regulator_platform_data to the tps68470-regulator MFD-cell platform/x86: int3472: Pass tps68470_clk_platform_data to the tps68470-regulator MFD-cell platform/x86: int3472: Add get_sensor_adev_and_name() helper platform/x86: int3472: Split into 2 drivers platform_data: Add linux/platform_data/tps68470.h file i2c: acpi: Add i2c_acpi_new_device_by_fwnode() function i2c: acpi: Use acpi_dev_ready_for_enumeration() helper ACPI: delay enumeration of devices with a _DEP pointing to an INT3472 device * clk-stm: clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell * clk-amlogic: clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB * clk-allwinner: clk: sunxi-ng: Add support for the D1 SoC clocks clk: sunxi-ng: gate: Add macros for gates with fixed dividers clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw dt-bindings: clk: Add compatibles for D1 CCUs clk: sunxi-ng: Allow the CCU core to be built as a module clk: sunxi-ng: Convert early providers to platform drivers clk: sunxi-ng: Allow drivers to be built as modules clk: sunxi-ng: Export symbols used by CCU drivers
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Stephen Boyd authored
* clk-doc: clk: Gemini: fix struct name in kernel-doc clk: zynq: pll: Fix kernel-doc warnings clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1 * clk-renesas: (31 commits) clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions clk: renesas: r9a07g044: Add TSU clock and reset entry mmc: renesas_sdhi: Simplify an expression mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple() clk: renesas: cpg-mssr: Check return value of pm_genpd_init() clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple() clk: renesas: rzg2l: Check return value of pm_genpd_init() clk: renesas: r9a07g044: Add RSPI clock and reset entries clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV clk: renesas: rzg2l: Add CPG_PL1_DDIV macro mmc: renesas_sdhi: Parse DT for SDnH mmc: renesas_sdhi: Use dev_err_probe when getting clock fails ... * clk-at91: clk: lan966x: Extend lan966x clock driver for clock gating support dt-bindings: clock: lan966x: Extend includes with clock gates dt-bindings: clock: lan966x: Extend for clock gate support clk: gate: Add devm_clk_hw_register_gate() clk: lan966x: Add lan966x SoC clock driver dt-bindings: clock: lan966x: Add LAN966X Clock Controller dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs * clk-cleanup: clk: stm32mp1: remove redundant assignment to pointer data clk: __clk_core_init() never takes NULL clk: clk_core_get() can also return NULL clk/ti/adpll: Make const pointer error a static const array * clk-debugfs: clk: Enable/Disable runtime PM for clk_summary clk: Emit a stern warning with writable debugfs enabled clk: Add write operation for clk_parent debugfs node
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- 07 Jan, 2022 5 commits
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Ajit Kumar Pandey authored
In newer SoC we have to clear bit for disabling 48MHz oscillator clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable and disable of 48MHz clock. Signed-off-by:
Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Reviewed-by:
Mario Limonciello <Mario.Limonciello@amd.com> Link: https://lore.kernel.org/r/20211212180527.1641362-6-AjitKumar.Pandey@amd.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Ajit Kumar Pandey authored
Replace hard coded con_id string with fch_data->name. We have clk consumers looking up with different clock names, hence use dynamic con_id string during clk lookup registration. fch_data->name will be initialized in acpi driver based on fmw property value. Signed-off-by:
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Ajit Kumar Pandey authored
Add a new device property to fetch clk-name from firmware. Signed-off-by:
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Ajit Kumar Pandey authored
Initially "is-rv" device property is added for 48MHz fixed clock support on Raven or RV architecture. It's unused now as we moved to pci device_id based selection to extend such support on other architectures. This change removed unused code from acpi driver. Signed-off-by:
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Ajit Kumar Pandey authored
FCH controller clock configuration slightly differs across AMD's SOC architectures. Newer family of SOC only support a 48MHz fix clock while stoney SOC family has a clk_mux to choose 48MHz and 25 MHz clk. At present fixed clk support is only enabled for RV architecture using "is-rv" device property initialized from boot loader. This limit 48MHz fixed clock gate support to RV platform unless we add similar device property in boot loader for other architectures. Add pci_device_id table with Stoney platform id and replace "is-rv" device property check with pci id match to add clk mux support with 25MHz and 48MHz clk support based on clk mux selection. This enable 48Mhz fixed fch clock support by default on all newer SOC's except stoney. Also replace RV with FIXED as a generic naming conventions across all platforms and changed module description. Signed-off-by:
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- 06 Jan, 2022 4 commits
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Taniya Das authored
The registers for some clocks in the SOC area, which are under the power domain are required to be enabled before accessing them. During the clk_summary if the power-domains are not enabled they could result into NoC errors. Thus ensure the register access of the clock controller is done with pm_untime_get/put functions. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1640018638-19436-3-git-send-email-tdas@codeaurora.orgSigned-off-by:
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Stephen Boyd authored
Merge tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull qcom clk driver updates from Bjorn Andersson: This introduces bindings and drivers for the global clock controllers found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for SDX65 and SM8450. It cleans up the SMD RPM clock driver and it adds includes for clk-provider.h throughout the clock providers that was lacking this. * tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits) clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock clk: qcom: smd-rpm: Drop the use of struct rpm_cc clk: qcom: smd-rpm: Drop MFD qcom-rpm reference ...
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Taniya Das authored
The gcc cfg noc lpass clock is required to be always enabled for the LPASS core and audio drivers to be functional. Fixes: a3cc0921 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by:
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Taniya Das authored
PLL poll for lock detection can take more than 100us for certain type of Lucid PLLs and also the new PLLs types(Lucid EVO), thus update to 200us. Signed-off-by:
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- 04 Jan, 2022 1 commit
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Stephen Boyd authored
Merge tag 'clk-v5.17-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - refactoring of the CPU clocks registration to use common interface - an update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) * tag 'clk-v5.17-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks clk: samsung: exynos850: Register clocks early clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: samsung: Update CPU clk registration clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks
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- 29 Dec, 2021 5 commits
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Stephen Boyd authored
Merge tag 'clk-imx-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Set suppress_bind_attrs to true for i.MX8ULP driver - Switch from do_div to div64_ul for throughout all drivers - Fix imx8mn_clko1_sels for i.MX8MN - Remove unused IPG_AUDIO_ROOT from i.MX8MP - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver * tag 'clk-imx-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx8mp: Fix the parent clk of the audio_root_clk clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h clk: imx8mn: Fix imx8mn_clko1_sels clk: imx: Use div64_ul instead of do_div clk: imx: imx8ulp: set suppress_bind_attrs to true
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Stephen Boyd authored
Merge tag 'for-5.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia Pull Tegra clk driver updates from Thierry Reding: This contains a simple fix for the VDE clock on Tegra114 and some preparation work to support runtime PM and generic power domains. * tag 'for-5.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-5.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Maxime Ripard: Our usual PR for the Allwinner SoCs, this time enabling our sub-framework to be built as a module, converting most drivers to platform drivers and allow them to be built as modules, and support for the Allwinner D1 * tag 'sunxi-clk-for-5.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Add support for the D1 SoC clocks clk: sunxi-ng: gate: Add macros for gates with fixed dividers clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw dt-bindings: clk: Add compatibles for D1 CCUs clk: sunxi-ng: Allow the CCU core to be built as a module clk: sunxi-ng: Convert early providers to platform drivers clk: sunxi-ng: Allow drivers to be built as modules clk: sunxi-ng: Export symbols used by CCU drivers
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https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull an Amlogic clock driver update from Jerome Brunet: - Fix MPLL0 gxbb SDM enable * tag 'clk-meson-v5.17-1' of https://github.com/BayLibre/clk-meson: clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB
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- 21 Dec, 2021 8 commits
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-9-vkoul@kernel.org
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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Vinod Koul authored
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by:
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- 19 Dec, 2021 7 commits
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David Virag authored
This is an initial implementation adding basic clocks, such as UART, USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which was made by Sam Protsenko, thus the copyright and author lines were kept. Bus clocks are enabled by default as well to avoid hangs while trying to access CMU registers. Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of CMU_CORE, and most of CMU_PERI is implemented as of now. Signed-off-by:
David Virag <virag.david003@gmail.com> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211206153124.427102-7-virag.david003@gmail.com
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David Virag authored
pll1417x is used in Exynos7885 SoC for top-level integer PLLs. It is similar enough to pll0822x that practically the same code can handle both. The difference that's to be noted is that when defining a pl1417x PLL, the "con" parameter of the PLL macro should be set to the CON1 register instead of CON3, like this: PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL), Signed-off-by:Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com
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David Virag authored
Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it to a new file called "clk-exynos-arm64.c". This should have no functional changes, but it will allow this code to be shared between other arm64 Exynos SoCs, like the Exynos7885 and possibly ExynosAuto V9. Signed-off-by:
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David Virag authored
Provide dt-schema documentation for Exynos7885 SoC clock controller. Description is modified from Exynos850 clock controller documentation as I couldn't describe it any better, that was written by Sam Protsenko. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211206153124.427102-3-virag.david003@gmail.com
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David Virag authored
Just like on Exynos850, the clock controller driver is designed to have separate instances for each particular CMU, so clock IDs start from 1 for each CMU in this bindings header too. Signed-off-by:
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Sam Protsenko authored
System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211217161549.24836-3-semen.protsenko@linaro.org
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Sam Protsenko authored
System Register is used to configure system behavior, like USI protocol, etc. SYSREG clocks should be provided to corresponding syscon nodes, to make it possible to modify SYSREG registers. While at it, add also missing PMU and GPIO clocks, which looks necessary and might be needed for corresponding Exynos850 features soon. Signed-off-by:
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- 16 Dec, 2021 7 commits
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AngeloGioacchino Del Regno authored
Add support for the global clock controller found on MSM8956 and MSM8976 SoCs. Since the multimedia clocks are actually in the GCC on these SoCs, this will allow drivers to probe and control basically all the required clocks. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Co-developed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Marijn Suijten authored
Document the required properties and firmware clocks for gcc-msm8976 to operate nominally, and add header definitions for referencing the clocks from firmware. Signed-off-by:
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Vinod Koul authored
This adds Global Clock controller (GCC) driver for SM8450 SoC including the gcc resets and gdsc. This patch is based on initial code downstream by Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by:
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Bjorn Andersson authored
v5.16-rc1 + 20211207114003.100693-2-vkoul@kernel.org The immutable branch contains the DT binding and clock defines as need for the Qualcomm SM8450 global clock controller driver.
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Vamsi Krishna Lanka authored
Add Global Clock Controller (GCC) support for SDX65 SoCs from Qualcomm. Signed-off-by:
Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Reviewed-by:
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Vamsi Krishna Lanka authored
Add a LUCID_EVO PLL type for SDX65 SoC from Qualcomm. Signed-off-by:
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Bjorn Andersson authored
Merge tag 'e15509b2b7c9b600ab38c5269d4fac609c077b5b.1638861860.git.quic_vamslank@quicinc.com' into clk-for-5.17 v5.16-rc1 + e15509b2b7c9b600ab38c5269d4fac609c077b5b.1638861860.git.quic_vamslank@quicinc.com Merge the immutable branch containing the DT binding and clock definitions needed for the SDX65 global clock controller driver.
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