- 11 Mar, 2022 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2022-03-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Reduce overzealous alignment constraints for GGTT - Add missing mdev attribute "name" for GVT - Async flip fixes (Ville) - Static checker fix (Ville) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YimvoLOZ8RPKrITv@jlahtine-mobl.ger.corp.intel.com
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- 09 Mar, 2022 6 commits
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Dave Airlie authored
Merge tag 'amd-drm-next-5.18-2022-03-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.18-2022-03-09: amdgpu: - Misc code cleanups - Misc display fixes - PSR display fixes - More RAS cleanup - Hotplug fix - Bump minor version for hotplug tests - SR-IOV fixes - GC 10.3.7 updates - Remove some firmwares which are no longer used - Mode2 reset refactor - Aldebaran fixes - Add VCN fwlog feature for VCN debugging - CS code cleanup - Fix clang warning - Fix CS clean up rebase breakage amdkfd: - SVM fixes - SMI event fixes and cleanups - vmid_pasid mapping fix for gfx10.3 Signed-off-by:
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
Follow-up pull req for v5.18 to pull in some important fixes. Signed-off-by:
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Lang Yu authored
It should be p->job->ibs[j] instead of p->job->ibs[i] here. Fixes: cdc7893f ("drm/amdgpu: use job and ib structures directly in CS parsers") Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yifan Zhang authored
it makes no sense to continue with an undefined vmid. Fixes: c8b0507f ("drm/amdkfd: judge get_atc_vmid_pasid_mapping_info before call") Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reported-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'exynos-drm-next-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next New feature - Add BGR pixel format support for FIMD device. As for this, this patch uses undocumented register, WIN_RGB_ORDER, but it is safe because product kernels have been using same register. Signed-off-by:
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Matthew Auld authored
Currently this will enforce both 2M alignment and padding for any LMEM pages inserted into the GGTT. However, this was only meant to be applied to the compact-pt layout with the ppGTT. For the GGTT we can reduce the alignment and padding to 64K. Bspec: 45015 Fixes: 87bd701e ("drm/i915: enforce min GTT alignment for discrete cards") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Robert Beckett <bob.beckett@collabora.com> Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220303100229.839282-1-matthew.auld@intel.com (cherry picked from commit c64fa77d) Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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- 08 Mar, 2022 7 commits
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Rob Clark authored
Avoid going down devfreq paths on devices where devfreq is not initialized. v2: Change has_devfreq() logic [Dmitry] Reported-by:
Linux Kernel Functional Testing <lkft@linaro.org> Reported-by:
Anders Roxell <anders.roxell@linaro.org> Signed-off-by:
Rob Clark <robdclark@chromium.org> Fixes: 6aa89ae1 ("drm/msm/gpu: Cancel idle/boost work on suspend") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220308184844.1121029-1-robdclark@gmail.com
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Dan Carpenter authored
These casts need to happen before the shift. The only time it would matter would be if "rev.core" is >= 128. In that case the sign bit would be extended and we do not want that. Fixes: afab9d91 ("drm/msm/adreno: Expose speedbin to userspace") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Link: https://lore.kernel.org/r/20220307133105.GA17534@kiliSigned-off-by:
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https://github.com/intel/gvt-linuxJoonas Lahtinen authored
- add the missing attribute "name" in VFIO mdev hierarchy. Signed-off-by:
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Ville Syrjälä authored
The current implementation of the async flip wm0/ddb optimization does not work at all. The biggest problem is that we skip the whole intel_pipe_update_{start,end}() dance and thus never actually complete the commit that is trying to do the wm/ddb change. To fix this we need to move the do_async_flip flag to the crtc state since we handle commits per-pipe, not per-plane. Also since all planes can now be included in the first/last "async flip" (which gets converted to a sync flip to do the wm/ddb mangling) we need to be more careful when checking if the plane state is async flip comptatible. Only planes doing the async flip should be checked and other planes are perfectly fine not adhereing to any async flip related limitations. However for subsequent commits which are actually going do the async flip in hardware we want to make sure no other planes are in the state. That should never happen assuming we did our job correctly, so we'll toss in a WARN to make sure we catch any bugs here. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220214105532.13049-4-ville.syrjala@linux.intel.comReviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (cherry picked from commit 2e084371) Signed-off-by:
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Ville Syrjälä authored
Since the async flip state check is done very late and thus it can see potentially all the planes in the state (due to the wm/ddb optimization) we need to move the "can the requested plane do async flips at all?" check much earlier. For this purpose we introduce intel_async_flip_check_uapi() that gets called early during the atomic check. And for good measure we'll throw in a couple of basic checks: - is the crtc active? - was a modeset flagged? - is+was the plane enabled? Though atm all of those should be guaranteed by the fact that the async flip can only be requested through the legacy page flip ioctl. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:
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Ville Syrjälä authored
data_rate==0 no longer means a plane is disabled, it could also mean we want to use the minimum ddb allocation for it. Hence we can't bail out early during ddb allocation or else we'll simply forget to allocate any ddb for such planes. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: 6a4d8cc6 ("drm/i915: Don't allocate extra ddb during async flip for DG2") Signed-off-by:
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Ville Syrjälä authored
bigjoiner_pipes==0 leads bigjoiner_master_pipe() to do BIT(ffs(0)-1) which is undefined behaviour. The code should actually still work fine since the only place we provoke that is intel_crtc_bigjoiner_slave_pipes() and it'll bitwise AND the result with 0, so doesn't really matter what we get out of bigjoiner_master_pipe(). But best not provoke undefined behaviour anyway. Reported-by:
kernel test robot <oliver.sang@intel.com> Fixes: a6e7a006 ("drm/i915: Change bigjoiner state tracking to use the pipe bitmask") Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> (cherry picked from commit cccc71b5) Signed-off-by:
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- 07 Mar, 2022 3 commits
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Philip Yang authored
To enable compiler type-checked against the format string in callers. All warnings (new ones prefixed by >>): >> warning: function 'kfd_smi_event_add' might be a candidate for 'gnu_printf' format attribute [-Wsuggest-attribute=format] Fixes: d58b8a99 ("drm/amdkfd: Add SMI add event helper") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Zhi Wang authored
The mdev attribute "name" is required by some middle software, e.g. KubeVirt, an open source SW that manages VM on Kubernetes cluster uses the mdev sysfs directory/file structure to discover mediated device in nodes in the cluster. v2: - Fix the missing defination in gvt_type_attrs. (Zhenyu) Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Hui Chun Ong <hui.chun.ong@intel.com> Cc: Terrence Xu <terrence.xu@intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by:
Zhi Wang <zhi.wang.linux@gmail.com> Link: http://patchwork.freedesktop.org/patch/msgid/20220222150532.9090-1-zhi.a.wang@intel.comReviewed-by:
Zhenyu Wang <zhenyuw@linux.intel.com>
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Rob Clark authored
refcount_t complains about 0->1 transitions, which isn't *quite* what we wanted. So use dirtyfb==1 to mean that the fb is not connected to any output that requires dirtyfb flushing, so that we can keep the underflow and overflow checking. Fixes: 9e4dde28 ("drm/msm: Avoid dirtyfb stalls on video mode displays (v2)") Signed-off-by:
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- 05 Mar, 2022 2 commits
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Rob Clark authored
Fixes: f6d62d09 ("drm/msm/a6xx: add support for Adreno 660 GPU") Signed-off-by:
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Rob Clark authored
Add a way for userspace to specify the sequence number fence used to track completion of the submit. As the seqno fence is simply an incrementing counter which is local to the submitqueue, it is easy for userspace to know the next value. This is useful for native userspace drivers in a vm guest, as the guest to host roundtrip can have high latency. Assigning the fence seqno in the guest userspace allows the guest to continue without waiting for response from the host. Signed-off-by:
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- 04 Mar, 2022 21 commits
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Rob Clark authored
Any app controlled perfcntr collection (GL_AMD_performance_monitor, etc) does not require counters to maintain state across context switches. So clear them if systemwide profiling is not active. Signed-off-by:
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Rob Clark authored
Add a SYSPROF param for system profiling tools like Mesa's pps-producer (perfetto) to control behavior related to system-wide performance counter collection. In particular, for profiling, one wants to ensure that GPU context switches do not effect perfcounter state, and might want to suppress suspend (which would cause counters to lose state). v2: Swap the order in msm_file_private_set_sysprof() [sboyd] and initialize the sysprof_active refcount to one (because the under/ overflow checking in refcount_t doesn't expect a 0->1 transition) meaning that values greater than 1 means sysprof is active. Signed-off-by: -
Rob Clark authored
It was always expected to have a use for this some day, so we left a placeholder. Now we do. (And I expect another use in the not too distant future when we start allowing userspace to allocate GPU iova.) Signed-off-by:
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Rob Clark authored
Update headers from mesa commit: commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef Author: Rob Clark <robclark@freedesktop.org> AuthorDate: Wed Mar 2 17:11:10 2022 -0800 freedreno/registers: Add a couple regs we need for kernel Signed-off-by:Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20220304005317.776110-2-robdclark@gmail.com
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Christian König authored
This way we don't need to check for NULL any more. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Christian König authored
We now have standard macros for that. Signed-off-by:
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Christian König authored
Instead of providing the ib index provide the job and ib pointers directly to the patch and parse functions for UVD and VCE. Also move the set/get functions for IB values to the IB declerations. Signed-off-by:
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Christian König authored
No function change, just move a bunch of definitions from amdgpu.h into separate header files. Signed-off-by:
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Jingwen Chen authored
[Why] after the reset domain introduced, the sched.ready will be init after hw_init, which will overwrite the setup in vcn hw_init, and lead to vcn ib test fail. [How] set disabled vcn to no_scheduler Fixes: 5fd8518d ("drm/amdgpu: Move scheduler init to after XGMI is ready") Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by:
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Christian König authored
Since we removed the context lock we need to make sure that not two threads are trying to install an entity at the same time. Signed-off-by:
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Yifan Zhang authored
This patch implements get_atc_vmid_pasid_mapping_info for gfx10.3 Signed-off-by:
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Yifan Zhang authored
Fix the NULL point issue: [ 3076.255609] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 3076.255624] #PF: supervisor instruction fetch in kernel mode [ 3076.255637] #PF: error_code(0x0010) - not-present page [ 3076.255649] PGD 0 P4D 0 [ 3076.255660] Oops: 0010 [#1] SMP NOPTI [ 3076.255669] CPU: 20 PID: 2415 Comm: kfdtest Tainted: G W OE 5.11.0-41-generic #45~20.04.1-Ubuntu [ 3076.255691] Hardware name: AMD Splinter/Splinter-RPL, BIOS VS2326337N.FD 02/07/2022 [ 3076.255706] RIP: 0010:0x0 [ 3076.255718] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [ 3076.255732] RSP: 0018:ffffb64283e3fc10 EFLAGS: 00010297 [ 3076.255744] RAX: 0000000000000000 RBX: 0000000000000008 RCX: 0000000000000027 [ 3076.255759] RDX: ffffb64283e3fc1e RSI: 0000000000000008 RDI: ffff8c7a87f60000 [ 3076.255776] RBP: ffffb64283e3fc78 R08: ffff8c7d88518ac0 R09: ffffb64283e3fa60 [ 3076.255791] R10: 0000000000000001 R11: 0000000000000001 R12: 000000000000000f [ 3076.255805] R13: ffff8c7bdcea5800 R14: ffff8c7a9f3f3000 R15: ffff8c7a8696bc00 [ 3076.255820] FS: 0000000000000000(0000) GS:ffff8c7d88500000(0000) knlGS:0000000000000000 [ 3076.255839] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3076.255851] CR2: ffffffffffffffd6 CR3: 0000000109e3c000 CR4: 0000000000750ee0 [ 3076.255866] PKRU: 55555554 [ 3076.255873] Call Trace: [ 3076.255884] dbgdev_wave_reset_wavefronts+0x72/0x160 [amdgpu] [ 3076.256025] process_termination_cpsch.cold+0x26/0x2f [amdgpu] [ 3076.256182] ? ktime_get_mono_fast_ns+0x4e/0xa0 [ 3076.256196] kfd_process_dequeue_from_all_devices+0x49/0x70 [amdgpu] [ 3076.256328] kfd_process_notifier_release+0x187/0x2b0 [amdgpu] [ 3076.256451] ? mn_itree_inv_end+0xdc/0x110 [ 3076.256463] __mmu_notifier_release+0x74/0x1f0 [ 3076.256474] exit_mmap+0x170/0x200 [ 3076.256484] ? __handle_mm_fault+0x677/0x920 [ 3076.256496] ? _cond_resched+0x19/0x30 [ 3076.256507] mmput+0x5d/0x130 [ 3076.256518] do_exit+0x332/0xaf0 [ 3076.256526] ? handle_mm_fault+0xd7/0x2b0 [ 3076.256537] do_group_exit+0x43/0xa0 [ 3076.256548] __x64_sys_exit_group+0x18/0x20 [ 3076.256559] do_syscall_64+0x38/0x90 [ 3076.256569] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by:
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Ruijing Dong authored
vcn fwlog is for debugging purpose only, by default, it is disabled. Signed-off-by:
Ruijing Dong <ruijing.dong@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Ruijing Dong authored
Add fw log in fw shared data structure. Reviewed-by:
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David Yu authored
Add DFC CAP support for aldebaran Initialize cap microcode in psp_init_sriov_microcode, the ta microcode will be initialized in psp_vxx_init_microcode Signed-off-by:
David Yu <David.Yu@amd.com> Reviewed-by:
Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
Aldebaran has 48-bit physical address support Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Lijo Lazar authored
Use IP version and refactor reset logic to apply to a list of devices. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Aric Cyr authored
drm/amd/display: 3.2.175 This version brings along following fixes: - Remove invalid RDPCS Programming in DAL - Make functional resource functions non-static - Reset VIC if HDMI_VIC is present - Add frame alternate 3D & restrict HW packed on dongles - Reg to turn on/off PSR Power seq in FSM - Modify plane removal sequence to avoid hangs - Pass HostVM enable flag into DCN3.1 DML - DC Validation failures - Program OPP before ODM - Refactor fixed VS w/a for PHY tests - Pass deep sleep disabled allow info to dmub fw - Refine the EDID override - [FW Promotion] Release 0.0.106.0 - Add verify_link_cap back for hdmi Acked-by:Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Charlene Liu authored
[why] hdmi specific: add verify link cap after retrive link cap. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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jinzh authored
[Why] We already get the SBIOS EDID via ACPI on KMD, but after that, we just use the monitor EDID to set it HDR caps [How] Make the SBIOS EDID override to read_edid() That can change the read EDID caps from the right EDID Reviewed-by:
jinzh <jinzh@github.amd.com> Tested-by:
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