- 23 Sep, 2021 2 commits
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Nirmoy Das authored
Pass drm dev directly as rdev->ddev gets initialized later on at radeon_device_init(). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214375Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Current RUNPM mechanism relies on PMFW to master the timing for BACO in/exit. And that needs cooperation from sound driver for dstate change notification for function 1(audio). Otherwise(on sound driver missing), BACO cannot be kicked in correctly and hang will be observed on RUNPM exit. By switching back to legacy message way on sound driver missing, we are able to fix the runpm hang observed for the scenario below: amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded Signed-off-by:
Evan Quan <evan.quan@amd.com> Reported-and-tested-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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- 14 Sep, 2021 38 commits
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xinhui pan authored
Direct IB submission should be exclusive. So use write lock. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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xinhui pan authored
alloc extra msg from direct IB pool. Signed-off-by:
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xinhui pan authored
alloc extra msg from direct IB pool. Signed-off-by:
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xinhui pan authored
move BO allocation in sw_init. Signed-off-by:
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Candice Li authored
Remove all TA binary structures and add the specific binary structure in struct ta_context. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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James Zhu authored
Separate iommu_resume from kfd_resume, and move it before other amdgpu ip init/resume. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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James Zhu authored
Add amdgpu_amdkfd_resume_iommu for amdgpu. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277Signed-off-by:
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James Zhu authored
Separate kfd_iommu_resume from kfd_resume for fine-tuning of amdgpu device init/resume/reset/recovery sequence. v2: squash in fix for !CONFIG_HSA_AMD Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277Signed-off-by:
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shaoyunl authored
The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies to all associated VFs. so guest driver can not directly enable the atomicOps for VF, it depends on PF to enable it. In current design, amdgpu driver will get the enabled atomicOps bits through private pf2vf data Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Michael Strauss authored
[WHY] Sequences to handle powering down these sub-IP blocks are now ready for use Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Ian Chen authored
Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Power down VPG and AFMT blocks when not in use [HOW] Create afmt31 and vpg31 structs and add necessary fields to reg list Reviewed-by:
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Jaehyun Chung authored
[Why] Degamma coefficients are calculated in our degamma formula using the regamma coefficients. We do not need to add separate degamma coefficients. [How] Remove the change to add separate degamma coefficients. Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Jaehyun Chung <jaehyun.chung@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] If link training is aborted, it shall be retried if sink is present. [How] Check hpd status to find out whether sink is present or not. If sink is present, then link training shall be tried again with same settings. Otherwise, link training shall be aborted. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Qingqing Zhuo authored
[Why] Intermittently, there presents two occurrences of 0 stream commits in a single HPD event. Current HDCP sequence does not consider such scenerio, and will thus disable HDCP. [How] Add condition check to include stream remove and re-enable case for HDCP enable. Reviewed-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Aric Cyr authored
* Correct degamma coefficients * Optimize bandwidth on following fast update * Fix multiple memory leaks reported by coverity * Get backlight from PWM if DMCU is not initialized Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Jaehyun Chung authored
[Why] Some incorrect coefficients were being used Reviewed-by:
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Anthony Koo authored
* PSR SMU optimizations * MST dock fixes Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Yang authored
[Why] When system is in Z10 HPD interrupts cannot fire, we may miss display configuration changes. [How] When Zstate is enabled, if DMUB indicate DCN has lost power, do a complete detection periodically. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Hersen Wu authored
[Why] call stack of amdgpu dsc mst pbn, slot num calculation is as below: -compute_bpp_x16_from_target_bandwidth -decide_dsc_target_bpp_x16 -setup_dsc_config -dc_dsc_compute_bandwidth_range -compute_mst_dsc_configs_for_link -compute_mst_dsc_configs_for_state from pbn -> dsc target bpp_x16 bpp_x16 is calulated by compute_bpp_x16_from_target_bandwidth. Beside pixel clock and bpp, num_slices_h and bpp_increment_div will also affect bpp_x16. from dsc target bpp_x16 -> pbn within dm_update_mst_vcpi_slots_for_dsc, pbn = drm_dp_calc_pbn_mode(clock, bpp_x16, true); drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), 8 * 54 * 1000 * 1000); } bpp / 16 trunc digits after decimal point. This will cause calculation delta. drm_dp_calc_pbn_mode does not have other informations, like num_slices_h, bpp_increment_div. therefore, it does not do revese calcuation properly from bpp_x16 to pbn. pbn from drm_dp_calc_pbn_mode is less than pbn from compute_mst_dsc_configs_for_state. This cause not enough mst slot allocated to display. display could not visually light up. [How] pass pbn from compute_mst_dsc_configs_for_state to dm_update_mst_vcpi_slots_for_dsc Cc: stable@vger.kernel.org Reviewed-by:Scott Foster <Scott.Foster@amd.com> Acked-by:
Hersen Wu <hersenwu@amd.com> Tested-by:
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Dale Zhao authored
[Why] In some scenarios like fullscreen game, major plane is scaled. Then if a upper layer owns the cursor, cursor is invisiable in the majority of the screen. [How] Instead assuming upper plane handles cursor, summing up upper split planes on the same layer. If whole upper plane covers current half/whole pipe plane, disable cursor. Reviewed-by:
Dale Zhao <dale.zhao@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] The current call to optimize_bandwidth never occurs because flip is always pending from the FULL and FAST updates. [How] Optimize on the following flip when it's a FAST update and we know we aren't going to be modifying the clocks again. Reviewed-by:
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Qingqing Zhuo authored
[Why] HPD disable and enable sequences are not mutually exclusive on Linux. For HPDs that spans under 1s (i.e. HPD low = 1s), part of the disable sequence (specifically, a request to SMU to lower refclk) could come right before the call to PHY enablement, causing DMUB to access an irresponsive PHY and thus a hard hang on the system. [How] Disable 48mhz refclk off when there is any HPD status in connected state. Reviewed-by:
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Jaehyun Chung authored
[Why] In YUV case, need to set the input TF to sRGB instead of BT709, even though the input TF type is distributed. SRGB was not being used because pixel format was not being set in the surface update sequence. Also, we were using the same coefficients for degamma and regamma formula, causing the cutoff point of the linear section of the curve to be incorrect. [How] Set pixel format in the surface update sequence. Add separate coefficient arrays for regamma and degamma. Reviewed-by:
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Anson Jacob authored
This reverts commit f5b6a20c. This patch broke new settings from taking effect. Hotplug is required for new settings to take effect. Reviewed-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
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Harry Wentland authored
On Carrizo/Stoney systems we set backlight through panel_cntl, i.e. directly via the PWM registers, if DMCU is not initialized. We always read it back through ABM registers which leads to a mismatch and forces atomic_commit to program the backlight each time. Instead make sure we use the same logic for backlight readback, i.e. read it from panel_cntl if DMCU is not initialized. We also need to remove some extraneous and incorrect calculations at the end of dce_get_16_bit_backlight_from_pwm. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1666 Cc: stable@vger.kernel.org Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Tested-by:
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Anson Jacob authored
coccinelle patch used: @@ expression enc1,vpg,afmt; @@ - if (!enc1 || !vpg || !afmt) + if (!enc1 || !vpg || !afmt) { + kfree(enc1); + kfree(vpg); + kfree(afmt); return NULL; + } Addresses-Coverity-ID: 1466017: ("Resource leaks") Reviewed-by:Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by:
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Aric Cyr authored
* coverity kernel memory leak fixes * NULL pointer dereference fixes * Add periodic detection when zstate is enabled * Fork thread to offload work of hpd_rx_irq Acked-by:
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Qingqing Zhuo authored
This reverts commit "drm/amd/display: w/a for hard hang on HPD on native DP". [How & Why] Revert change as it does not fix the hard hang in all cases. An alternative w/a will be submitted separately. Acked-by:
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Anthony Koo authored
* PSR optimizations * add support for ABM when ODM is enabled * Z10 with PSR fixes * Increase trace buffer Acked-by:
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Meenakshikumar Somasundaram authored
[Why] Need a check for NULL pointer access for ddc pin and aux engine. [How] Adding a check for ddc pin and aux engine accesses. Reviewed-by:
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Anson Jacob authored
This is an attempt to fix false warning raised by Coverity via multiple CID's. Addresses-Coverity-ID: 1487412 ("Free of address-of expression") Cc: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:Wesley Chalmers <wesley.chalmers@amd.com> Acked-by:
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Jimmy Kizito authored
[Why] Assuming DIG link encoders are statically mapped to links can cause system instability due to null pointer accesses. [How] - Add checks for non-null link encoder pointers before trying to access them. - When a hardware platform uses dynamic DIG assignment (i.e. resource function 'link_encs_assign' defined) and a link supports flexible mapping to DIGs, use the link_enc_cfg API to access the DIG assigned to a link or stream. Reviewed-by:
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Aurabindo Pillai authored
[Why] When a connector is unplugged, dpms is forced off so that some connector allocations are cleared off. This is done outside the commit sequence from the userspace. This causes HUBP blank. Due to the blank hubp, a non blocking commit which queues flip will encounter a timeout waiting for the flip_done because prior to writing the surface flip address, hubp was in blank. [How] Add a marker to DM's crtc state and use this field to indicate whether dpms was forced off during an HPD. Check for this marker before queuing the flip. Reviewed-by:
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Josip Pavic authored
[Why] When ODM is enabled, ABM is blocked on dcn31 but unblocked on dcn30. Since the dcn31 firmware is now able to handle ABM interop with ODM, it is no longer necessary to block ABM when ODM is enabled. Since the dcn30 firmware does not handle ABM interop with ODM, leaving that combination unblocked can lead to one side of the screen appearing brighter than the other. [How] When ODM is enabled, unblock abm on dcn31 and block it on dcn30 Reviewed-by:
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Wayne Lin authored
[Why] Currently, we will try to get dm.dc_lock in handle_hpd_rx_irq() when link lost happened, which is risky and could cause deadlock. e.g. If we are under procedure to enable MST streams and then monitor happens to toggle short hpd to notify link lost, then handle_hpd_rx_irq() will get blocked due to stream enabling flow has dc_lock. However, under MST, enabling streams involves communication with remote sinks which need to use handle_hpd_rx_irq() to handle sideband messages. Thus, we have deadlock here. [How] Target is to have handle_hpd_rx_irq() finished as soon as possilble. Hence we can react to interrupt quickly. Besides, we should avoid to grabe dm.dc_lock within handle_hpd_rx_irq() to avoid deadlock situation. Firstly, revert patches which introduced to use dm.dc_lock in handle_hpd_rx_irq(): * commit ("drm/amd/display: NULL pointer error during ") * commit ("drm/amd/display: Only one display lights up while using MST") * commit ("drm/amd/display: take dc_lock in short pulse handler only") Instead, create work to handle irq events which needs dm.dc_lock. Besides: * Create struct hpd_rx_irq_offload_work_queue for each link to handle its short hpd events * Avoid to handle link lost/ automated test if the link is disconnected * Defer dc_lock needed works in dc_link_handle_hpd_rx_irq(). This function should just handle simple stuff for us (e.g. DPCD R/W). However, deferred works should still be handled by the order that dc_link_handle_hpd_rx_irq() used to be. * Change function name dm_handle_hpd_rx_irq() to dm_handle_mst_sideband_msg() to be more specific Reviewed-by:Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Wayne Lin authored
[Why & How] Due to some code flow constraints, we need to defer dc_lock needed works from dc_link_handle_hpd_rx_irq(). Thus, do following changes: * Change allow_hpd_rx_irq() from static to public * Change handle_automated_test() from static to public * Extract link lost handling flow out from dc_link_handle_hpd_rx_irq() and put those into a new function dc_link_dp_handle_link_loss() * Add one option parameter to decide whether defer works within dc_link_handle_hpd_rx_irq() Acked-by:
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Wenjing Liu authored
[why] According to DP specs dfp cap ext validation is only for branch device withou 128b/132b channel coding support and downstream of the branch device doesn't have compression. Therefore we are adding conditions to only do dfp cap extension validation for branch devcie supporting 8b/10b channel coding only and it has no DSC passthrough capability. Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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