- 06 Mar, 2023 4 commits
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Mark Brown authored
Merge series from Claudiu Beznea <claudiu.beznea@microchip.com>: This series does some cleanups for Microchip AT91 sound drivers. Along with it I took the chance and updated MAINTAINERS file.
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Mark Brown authored
Merge series from Prabhakar <prabhakar.csengg@gmail.com>: Hi All, This patch series aims to fix interrupt numbers for SSI channels and updates the DT binding and the driver accordingly. Note, this patch series applies on top of [0]. [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20230131223529.11905-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (4): ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels .../bindings/sound/renesas,rz-ssi.yaml | 21 ++++--- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 19 +++--- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++--- sound/soc/sh/rz-ssi.c | 63 +++++++++++++------ 4 files changed, 70 insertions(+), 52 deletions(-) -- 2.25.1
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Mark Brown authored
Merge series from Peter Ujfalusi <peter.ujfalusi@linux.intel.com>: The first patch will improve the managing of DMI L1 by tracking it's enabled/disabled state to avoid unconditional changes to it's state. The remaining two patch will enable the DMI L1 for MTL platforms (ACE 1.0)
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Mark Brown authored
Merge series from Herve Codina <herve.codina@bootlin.com>: This series adds support for audio using the QMC controller available in some Freescale PowerQUICC SoCs. This series contains three parts in order to show the different blocks hierarchy and their usage in this support. The first one is related to TSA (Time Slot Assigner). The TSA handles the data present at the pin level (TDM with up to 64 time slots) and dispatchs them to one or more serial controller (SCC). The second is related to QMC (QUICC Multichannel Controller). The QMC handles the data at the serial controller (SCC) level and splits again the data to creates some virtual channels. The last one is related to the audio component (QMC audio). It is the glue between the QMC controller and the ASoC component. It handles one or more QMC virtual channels and creates one DAI per QMC virtual channels handled.
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- 05 Mar, 2023 36 commits
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Krzysztof Kozlowski authored
Convert the Qualcomm WCD9335 audio codec binding to DT schema. Changes against original binding: 1. Drop "mclk2" from clocks as neither Linux driver nor DTS uses it. 2. Do not require vdd-micbias-supply as several DTS do not provide it. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230220095643.64898-2-krzysztof.kozlowski@linaro.orgSigned-off-by:
Mark Brown <broonie@kernel.org>
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Krzysztof Kozlowski authored
Reference common DAI properties to get sound-dai-cells description and allow name-prefix. Signed-off-by:
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Svyatoslav Ryhel authored
This feature is required for coupled hp-mic quirk used by some Nvidia Tegra 3 based devices work properly. Signed-off-by:
Svyatoslav Ryhel <clamor95@gmail.com> Link: https://lore.kernel.org/r/20230221183211.21964-3-clamor95@gmail.comSigned-off-by:
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Kuninori Morimoto authored
There are no compatible for "reg/reg-names" and "clock-name" between previous R-Car series and R-Car Gen4. "reg/reg-names" needs 3 categorize (for Gen1, for Gen2/Gen3, for Gen4), therefore, use 3 if-then to avoid nested if-then-else. Move "clock-name" detail properties to under allOf to use if-then-else for Gen4 or others. Link: https://lore.kernel.org/all/87zg9vk0ex.wl-kuninori.morimoto.gx@renesas.com/#r Link: https://lore.kernel.org/all/87r0v2uvm7.wl-kuninori.morimoto.gx@renesas.com/#r Link: https://lore.kernel.org/all/87r0v1t02h.wl-kuninori.morimoto.gx@renesas.com/#r Link: https://lore.kernel.org/all/87y1p7bpma.wl-kuninori.morimoto.gx@renesas.com/#rReported-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
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Gustavo A. R. Silva authored
Zero-length arrays as fake flexible arrays are deprecated and we are moving towards adopting C99 flexible-array members, instead. Use the DECLARE_FLEX_ARRAY() helper macro to transform zero-length arrays in unions with flexible-array members. Address the following warnings found with GCC-13 and -fstrict-flex-arrays=3 enabled: sound/soc/sof/ipc4-control.c:176:77: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:78:29: warning: array subscript 0 is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:80:33: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:95:53: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:96:53: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:93:53: warning: array subscript 0 is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:140:58: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:141:29: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-control.c:142:29: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-topology.c:1475:36: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] sound/soc/sof/ipc4-topology.c:1476:36: warning: array subscript i is outside array bounds of ‘struct sof_ipc4_ctrl_value_chan[0]’ [-Warray-bounds=] This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/21 Link: https://github.com/KSPP/linux/issues/193 Link: https://github.com/KSPP/linux/issues/258 Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602902.html [1] Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Acked-by:
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Link: https://lore.kernel.org/r/Y/gyIg1qZduhigPi@workSigned-off-by:
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Seven Lee authored
This patch is support dynamic range compression controls. Signed-off-by:
Seven Lee <wtli@nuvoton.com> Signed-off-by:
Seven Lee <scott6986@gmail.com> Link: https://lore.kernel.org/r/20230217092523.357142-1-wtli@nuvoton.comSigned-off-by:
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Srinivas Kandagatla authored
Add Kcontrol to jack pins so that device switch in ucm can be done correctly. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20230302104616.26318-1-srinivas.kandagatla@linaro.orgSigned-off-by:
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Chancel Liu authored
Convert the Wolfson WM8524 24-bit 192KHz Stereo DAC device tree binding documentation to json-schema. Signed-off-by:
Chancel Liu <chancel.liu@nxp.com> Reviewed-by:
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Krzysztof Kozlowski authored
Convert the Wolfson WM8960 audio codecs bindings to DT schema. Changes against original binding: 1. Document clocks and clock-names - already present in DTS and used by Linux driver. Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230217150627.779764-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Jacob Keller authored
The struct avs_modcfg_ext structure has a flexible array member for the pin_fmts array, and the size should be calculated using struct_size to prevent the potential for overflow with the allocation. Reviewed-by:
Cezary Rojewski <cezary.rojewski@intel.com> Reviewed-by:
"Amadeusz Sławiński" <amadeuszx.slawinski@linux.intel.com> Signed-off-by:
Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20230303180457.2457069-1-jacob.e.keller@intel.comSigned-off-by:
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Claudiu Beznea authored
Add documentation files to Microchip AT91 sound entries. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20230301113807.24036-9-claudiu.beznea@microchip.comSigned-off-by:
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Claudiu Beznea authored
Codrin is not with Microchip anymore. As I worked lately with Microchip AT91 sound drivers add myself as maintainer for these. Signed-off-by:
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Claudiu Beznea authored
Do not cast to and from void pointer. There is no need for this. Signed-off-by:
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Claudiu Beznea authored
Return directly ret instead of having different branches for error and OK paths. Signed-off-by:
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Claudiu Beznea authored
Use FIELD_PREP() macro where possible instead of driver local defined macros. Signed-off-by:
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Claudiu Beznea authored
Previous debug message states that there was a failure and tx was not disabled. Which is not true as the TX in this function could also be enabled. Thus improve a bit the debug message by s/disable/start\/stop/. Signed-off-by:
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Claudiu Beznea authored
Use regmap_update_bits() instead of regmap_read(), running variable, regmap_write(). There is no need for extra variables and checks around it as regmap_update_bits() already does this. With this code becomes simpler. Signed-off-by:
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Claudiu Beznea authored
Use directly FIELD_PREP() marco where possible. There is no need for the extra wrappers. Signed-off-by:
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Ranjani Sridharan authored
DMI L1 should be enabled unconditionally after FW boot is complete. Signed-off-by:
Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by:
Rander Wang <rander.wang@intel.com> Reviewed-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by:
Bard Liao <yung-chuan.liao@linux.intel.com> Signed-off-by:
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Ranjani Sridharan authored
The workaround to disable DMI L1 should be restricted to only the CAVS IP's. Signed-off-by:
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Ranjani Sridharan authored
We have a workaround in place to address a known issue with host DMA running into xruns when capture streams are running. But when resuming from Sx, we unconditionally re-enable DMI L1 without taking the workaround into account and this could lead to xruns when a suspended capture stream is restarted. To fix this rename the flag l1_support_enabled to l1_disabled in struct sof_intel_hda_dev to save the L1 disabled status which can be set/cleared when we get/put a stream and use the flag to determine if DMI L1 should enabled or not during the post_fw_run op. Signed-off-by:
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Herve Codina authored
After contributing the component, add myself as the maintainer for the Freescale QMC audio ASoC component. Signed-off-by:
Herve Codina <herve.codina@bootlin.com> Reviewed-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20230217145645.1768659-11-herve.codina@bootlin.comSigned-off-by:
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Herve Codina authored
The QMC audio is an ASoC component which provides DAIs that use the QMC (QUICC Multichannel Controller) to transfer the audio data. It provides as many DAIs as the number of QMC channels it references. Signed-off-by:
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Herve Codina authored
The QMC (QUICC mutichannel controller) is a controller present in some PowerQUICC SoC such as MPC885. The QMC audio is an ASoC component that uses the QMC controller to transfer the audio data. Signed-off-by:
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Herve Codina authored
After contributing the driver, add myself as the maintainer for the Freescale QMC controller. Signed-off-by:
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Herve Codina authored
The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one serial controller using the same TDM physical interface routed from the TSA. It is available in some PowerQUICC SoC such as the MPC885 or MPC866. It is also available on some Quicc Engine SoCs. This current version support CPM1 SoCs only and some enhancement are needed to support Quicc Engine SoCs. Signed-off-by:
Li Yang <leoyang.li@nxp.com> Reviewed-by:
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Herve Codina authored
Add support for the QMC (QUICC Multichannel Controller) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by:
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Herve Codina authored
The CPM1 command mask is defined for use with the standard CPM1 command register as described in the user's manual: 0 |1 3|4 7|8 11|12 14| 15| RST| - |OPCODE|CH_NUM| - |FLG| In the QMC extension the CPM1 command register is redefined (QMC supplement user's manuel) with the following mapping: 0 |1 3|4 7|8 13|14| 15| RST|QMC OPCODE| 1110|CHANNEL_NUMBER| -|FLG| Extend the check command mask in order to support both the standard CH_NUM field and the QMC extension CHANNEL_NUMBER field. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230217145645.1768659-5-herve.codina@bootlin.comSigned-off-by:
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Herve Codina authored
After contributing the driver, add myself as the maintainer for the Freescale TSA controller. Signed-off-by:
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Herve Codina authored
The TSA (Time Slot Assigner) purpose is to route some TDM time-slots to other internal serial controllers. It is available in some PowerQUICC SoC such as the MPC885 or MPC866. It is also available on some Quicc Engine SoCs. This current version support CPM1 SoCs only and some enhancement are needed to support Quicc Engine SoCs. Signed-off-by:
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Herve Codina authored
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by:
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Lad Prabhakar authored
For half duplex channels we dont have separate interrupts for Tx and Rx instead we have single interrupt Rt (where the signal for Rx and Tx is muxed). To handle such a case install a handler in case we have a dma_rt interrupt specified in the DT for the PIO mode. Note, for backward compatibility we check if the Rx and Tx interrupts are present first instead of checking Rt interrupt. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230217185225.43310-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Lad Prabhakar authored
From R01UH0914EJ0120 Rev.1.20 HW manual, for full duplex channels (SSI0/1/3) dma_rt interrupt has now being marked as reserved and similarly for half duplex channel (SSI2) dma_rx and dma_tx interrupts have now being marked as reserved (this applies to RZ/G2L and alike SoC's). This patch updates the binding doc to match the same. While at it also updated the example node. Signed-off-by:
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Linus Torvalds authored
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Linus Torvalds authored
Commit aa47a7c2 ("lib/cpumask: deprecate nr_cpumask_bits") resulted in the cpumask operations potentially becoming hugely less efficient, because suddenly the cpumask was always considered to be variable-sized. The optimization was then later added back in a limited form by commit 6f9c07be ("lib/cpumask: add FORCE_NR_CPUS config option"), but that FORCE_NR_CPUS option is not useful in a generic kernel and more of a special case for embedded situations with fixed hardware. Instead, just re-introduce the optimization, with some changes. Instead of depending on CPUMASK_OFFSTACK being false, and then always using the full constant cpumask width, this introduces three different cpumask "sizes": - the exact size (nr_cpumask_bits) remains identical to nr_cpu_ids. This is used for situations where we should use the exact size. - the "small" size (small_cpumask_bits) is the NR_CPUS constant if it fits in a single word and the bitmap operations thus end up able to trigger the "small_const_nbits()" optimizations. This is used for the operations that have optimized single-word cases that get inlined, notably the bit find and scanning functions. - the "large" size (large_cpumask_bits) is the NR_CPUS constant if it is an sufficiently small constant that makes simple "copy" and "clear" operations more efficient. This is arbitrarily set at four words or less. As a an example of this situation, without this fixed size optimization, cpumask_clear() will generate code like movl nr_cpu_ids(%rip), %edx addq $63, %rdx shrq $3, %rdx andl $-8, %edx callq memset@PLT on x86-64, because it would calculate the "exact" number of longwords that need to be cleared. In contrast, with this patch, using a MAX_CPU of 64 (which is quite a reasonable value to use), the above becomes a single movq $0,cpumask instruction instead, because instead of caring to figure out exactly how many CPU's the system has, it just knows that the cpumask will be a single word and can just clear it all. Note that this does end up tightening the rules a bit from the original version in another way: operations that set bits in the cpumask are now limited to the actual nr_cpu_ids limit, whereas we used to do the nr_cpumask_bits thing almost everywhere in the cpumask code. But if you just clear bits, or scan for bits, we can use the simpler compile-time constants. In the process, remove 'cpumask_complement()' and 'for_each_cpu_not()' which were not useful, and which fundamentally have to be limited to 'nr_cpu_ids'. Better remove them now than have somebody introduce use of them later. Of course, on x86-64 with MAXSMP there is no sane small compile-time constant for the cpumask sizes, and we end up using the actual CPU bits, and will generate the above kind of horrors regardless. Please don't use MAXSMP unless you really expect to have machines with thousands of cores. Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds authored
Pull crypto fix from Herbert Xu: "Fix a regression in the caam driver" * tag 'v6.3-p2' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: caam - Fix edesc/iv ordering mixup
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