1. 20 May, 2016 25 commits
  2. 09 May, 2016 1 commit
    • Catalin Marinas's avatar
      kvm: arm64: Enable hardware updates of the Access Flag for Stage 2 page tables · 06485053
      Catalin Marinas authored
      The ARMv8.1 architecture extensions introduce support for hardware
      updates of the access and dirty information in page table entries. With
      VTCR_EL2.HA enabled (bit 21), when the CPU accesses an IPA with the
      PTE_AF bit cleared in the stage 2 page table, instead of raising an
      Access Flag fault to EL2 the CPU sets the actual page table entry bit
      (10). To ensure that kernel modifications to the page table do not
      inadvertently revert a bit set by hardware updates, certain Stage 2
      software pte/pmd operations must be performed atomically.
      
      The main user of the AF bit is the kvm_age_hva() mechanism. The
      kvm_age_hva_handler() function performs a "test and clear young" action
      on the pte/pmd. This needs to be atomic in respect of automatic hardware
      updates of the AF bit. Since the AF bit is in the same position for both
      Stage 1 and Stage 2, the patch reuses the existing
      ptep_test_and_clear_young() functionality if
      __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG is defined. Otherwise, the
      existing pte_young/pte_mkold mechanism is preserved.
      
      The kvm_set_s2pte_readonly() (and the corresponding pmd equivalent) have
      to perform atomic modifications in order to avoid a race with updates of
      the AF bit. The arm64 implementation has been re-written using
      exclusives.
      
      Currently, kvm_set_s2pte_writable() (and pmd equivalent) take a pointer
      argument and modify the pte/pmd in place. However, these functions are
      only used on local variables rather than actual page table entries, so
      it makes more sense to follow the pte_mkwrite() approach for stage 1
      attributes. The change to kvm_s2pte_mkwrite() makes it clear that these
      functions do not modify the actual page table entries.
      
      The (pte|pmd)_mkyoung() uses on Stage 2 entries (setting the AF bit
      explicitly) do not need to be modified since hardware updates of the
      dirty status are not supported by KVM, so there is no possibility of
      losing such information.
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      06485053
  3. 03 May, 2016 10 commits
  4. 29 Apr, 2016 1 commit
  5. 21 Apr, 2016 3 commits
    • Suzuki K Poulose's avatar
      arm64: kvm: Add support for 16K pages · 02e0b760
      Suzuki K Poulose authored
      Now that we can handle stage-2 page tables independent
      of the host page table levels, wire up the 16K page
      support.
      
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      02e0b760
    • Suzuki K Poulose's avatar
      kvm-arm: Cleanup stage2 pgd handling · 9163ee23
      Suzuki K Poulose authored
      Now that we don't have any fake page table levels for arm64,
      cleanup the common code to get rid of the dead code.
      
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      9163ee23
    • Suzuki K Poulose's avatar
      kvm: arm64: Get rid of fake page table levels · da04fa04
      Suzuki K Poulose authored
      On arm64, the hardware supports concatenation of upto 16 tables,
      at entry level for stage2 translations and we make use that whenever
      possible. This could lead to reduced number of translation levels than
      the normal (stage1 table) table. Also, since the IPA(40bit) is smaller
      than the some of the supported VA_BITS (e.g, 48bit), there could be
      different number of levels in stage-1 vs stage-2 tables. To reuse the
      kernel host page table walker for stage2 we have been using a fake
      software page table level, not known to the hardware. But with 16K
      translations, there could be upto 2 fake software levels (with 48bit VA
      and 40bit IPA), which complicates the code. Hence, we want to get rid of
      the hack.
      
      Now that we have explicit accessors for hyp vs stage2 page tables,
      define the stage2 walker helpers accordingly based on the actual
      table used by the hardware.
      
      Once we know the number of translation levels used by the hardware,
      it is merely a job of defining the helpers based on whether a
      particular level is folded or not, looking at the number of levels.
      
      Some facts before we calculate the translation levels:
      
      1) Smallest page size supported by arm64 is 4K.
      2) The minimum number of bits resolved at any page table level
         is (PAGE_SHIFT - 3) at intermediate levels.
      Both of them implies, minimum number of bits required for a level
      change is 9.
      
      Since we can concatenate upto 16 tables at stage2 entry, the total
      number of page table levels used by the hardware for resolving N bits
      is same as that for (N - 4) bits (with concatenation), as there cannot
      be a level in between (N, N-4) as per the above rules.
      
      Hence, we have
      
       STAGE2_PGTABLE_LEVELS = PGTABLE_LEVELS(KVM_PHYS_SHIFT - 4)
      
      With the current IPA limit (40bit), for all supported translations
      and VA_BITS, we have the following condition (even for 36bit VA with
      16K page size):
      
       CONFIG_PGTABLE_LEVELS >= STAGE2_PGTABLE_LEVELS.
      
      So, for e.g,  if PUD is present in stage2, it is present in the hyp(host).
      Hence, we fall back to the host definition if we find that a level is not
      folded. Otherwise we redefine it accordingly. A build time check is added
      to make sure the above condition holds. If this condition breaks in future,
      we can rearrange the host level helpers and fix our code easily.
      
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      da04fa04