- 24 Sep, 2020 9 commits
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Christian König authored
Stop using TTM_PL_FLAG_NO_EVICT. v2: fix unconditional pinning Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Link: https://patchwork.freedesktop.org/patch/391601/?series=81973&rev=1
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Christian König authored
Implement in the driver instead since it is the only user of that function. v2: fix usage of ttm_bo_init_reserved Signed-off-by:
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Christian König authored
Just some dead code cleanup. Signed-off-by:
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Christian König authored
As an alternative to the placement flag add a pin count to the ttm buffer object. v2: add dma_resv_assert_help() calls Signed-off-by:
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Thomas Zimmermann authored
The gamma LUT has to be reloaded after changing the primary plane's color format. This used to be done implicitly by the CRTC atomic_enable() helper after updating the primary plane. With the recent reordering of the steps, the primary plane's setup was moved last and invalidated the gamma LUT. Fix this by setting the LUT from within atomic_flush(). Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Fixes: 2f0ddd89 ("drm/ast: Enable CRTC before planes") Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dave Airlie <airlied@redhat.com> Cc: dri-devel@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20200922144655.23624-1-tzimmermann@suse.de
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Christian König authored
Not used any more. Cleanup the code as well while at it. Signed-off-by:
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Christian König authored
According to Ben this is most likely just a leftover. Signed-off-by:
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Jani Nikula authored
Prepare for future with DP 2.0 DPCD definitions, with a couple of related drive-by cleanups. No functional changes. v2: Send the version that actually builds. Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200918114017.30198-2-jani.nikula@intel.com
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Jani Nikula authored
Add the subheadings from the DP spec. No functional changes. Reviewed-by:
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- 23 Sep, 2020 8 commits
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Dave Airlie authored
I'm thinking of pushing the wait into the drivers. Reviewed-by:
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Dave Airlie authored
This just uses the ctx instead of passing bools and recreating it. Acked-by:
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Dave Airlie authored
Just pass it around move, and remove unused pieces Reviewed-by:
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Dave Airlie authored
This wasn't used anywheere Acked-by:
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Dave Airlie authored
this is unused Reviewed-by:
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Daniel Vetter authored
Even for legacy userspace, since otherwise GETFB2 is broken and if you switch between modifier-less and modifier-aware compositors, smooth transitions break. Also it's just best practice to make sure modifiers are invariant for a given drm_fb, and that a modifier-aware kms drivers only has one place to store them, ignoring any old implicit bo flags or whatever else might float around. Motivated by some irc discussion with Bas about amdgpu modifier support. Acked-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Acked-by:
Simon Ser <contact@emersion.fr> Acked-by:
Daniel Stone <daniels@collabora.com> Acked-by:
Pekka Paalanen <pekka.paalanen@collabora.com> Fixes: 455e00f1 ("drm: Add getfb2 ioctl") Cc: Daniel Stone <daniels@collabora.com> Cc: Juston Li <juston.li@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Marek Olšák <maraeo@gmail.com> Cc: "Wentland, Harry" <harry.wentland@amd.com> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200917164721.2038541-1-daniel.vetter@ffwll.ch
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Christian König authored
When we swapout/in a BO we try to change the caching attributes of the pages before/after doing the copy. On x86 this is done by calling set_pages_uc(), set_memory_wc() or set_pages_wb() for not highmem pages to update the linear mapping of the page. On all other platforms we do exactly nothing. Now on x86 this is unnecessary because copy_highpage() will either create a temporary mapping of the page which is wb anyway and destroyed immediately again or use the linear mapping with the correct caching attributes. So stop this nonsense and just keep the caching as it is and return an error when a driver tries to change the caching of an already populated TT object. This is much more defensive since changing caching attributes is platform and driver specific and usually doesn't work after the page was initially allocated. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/391293/
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Christian König authored
map_page_into_agp() and unmap_page_from_agp() are only defined on x86. On all other platforms they are defined as noops. So this code doesn't has any effect at all. Signed-off-by:
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- 22 Sep, 2020 4 commits
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Koba Ko authored
As per DP-1.3, First check DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT. If DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is 1,read the DP_DP13_DPCD_REV to get the faster capability. If DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is 0,read DP_DPCD_REV. Signed-off-by:
Koba Ko <koba.ko@canonical.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> [added aux name to drm_dbg_kms() call] Signed-off-by:
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Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by:
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Colin Ian King authored
There are a couple of statements that are indented too deeply, remove the extraneous tabs and also an empty line. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Thomas Zimmermann authored
Commit 7053e0ea ("drm/vram-helper: stop using TTM placement flags") cleared the BO placement flags if top-down placement had been selected. Hence, BOs that were supposed to go into VRAM are now placed in a default location in system memory. Trying to scanout the incorrectly pinned BO results in displayed garbage and an error message. [ 146.108127] ------------[ cut here ]------------ [ 146.1V08180] WARNING: CPU: 0 PID: 152 at drivers/gpu/drm/drm_gem_vram_helper.c:284 drm_gem_vram_offset+0x59/0x60 [drm_vram_helper] ... [ 146.108591] ast_cursor_page_flip+0x3e/0x150 [ast] [ 146.108622] ast_cursor_plane_helper_atomic_update+0x8a/0xc0 [ast] [ 146.108654] drm_atomic_helper_commit_planes+0x197/0x4c0 [ 146.108699] drm_atomic_helper_commit_tail_rpm+0x59/0xa0 [ 146.108718] commit_tail+0x103/0x1c0 ... [ 146.109302] ---[ end trace d901a1ba1d949036 ]--- Fix the bug by keeping the placement flags. The top-down placement flag is stored in a separate variable. Signed-off-by:
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- 21 Sep, 2020 11 commits
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Jason Yan authored
This eliminates the following sparse warning: drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c:217:15: warning: symbol 'vint_table' was not declared. Should it be static? While at it, make the table const as it is never modified. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Jason Yan <yanaijie@huawei.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200916132301.2914017-1-yanaijie@huawei.com
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Wang ShaoBo authored
Fix unused but set variable warning building with `make W=1`: drivers/gpu/drm/imx/dcss/dcss-plane.c:270:6: warning: variable ‘pixel_format’ set but not used [-Wunused-but-set-variable] u32 pixel_format; ^~~~~~~~~~~~ Fixes: 9021c317 ("drm/imx: Add initial support for DCSS on iMX8MQ") Reported-by:Wang ShaoBo <bobo.shaobowang@huawei.com> Reviewed-by:
Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200911014414.4663-1-bobo.shaobowang@huawei.com
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Maxime Ripard authored
The vc4 display engine has a first controller called the HVS that will perform the composition of the planes. That HVS has 3 FIFOs and can therefore compose planes for up to three outputs. The timings part is generated through a component called the Pixel Valve, and the BCM2711 has 6 of them. Thus, the HVS has some bits to control which FIFO gets output to which Pixel Valve. The current code supports that muxing by looking at all the CRTCs in a new DRM atomic state in atomic_check, and given the set of constraints that we have, assigns FIFOs to CRTCs or reject the mode entirely. The actual muxing will occur during atomic_commit. However, that doesn't work if only a fraction of the CRTCs' state is updated in that state, since it will ignore the CRTCs that are kept running unmodified, and will thus unassign its associated FIFO, and later disable it. In order to make the code work as expected, let's pull the CRTC state of all the enabled CRTC in our atomic_check so that we can operate on all the running CRTCs, no matter whether they are affected by the new state or not. Fixes: 87ebcd42 ("drm/vc4: crtc: Assign output to channel automatically") Signed-off-by:
Maxime Ripard <maxime@cerno.tech> Tested-by:
Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by:
Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by:
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Tian Tao authored
Update kernel-doc line comments to fix warnings reported by make W=1. drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'glob' not described in 'ttm_shrink' drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'from_wq' not described in 'ttm_shrink' drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'extra' not described in 'ttm_shrink' drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'ctx' not described in 'ttm_shrink' Signed-off-by:
Tian Tao <tiantao6@hisilicon.com> Reviewed-by:
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Neil Armstrong authored
This adds the required GPU quirks, including the quirk in the PWR registers at the GPU reset time and the IOMMU quirk for shareability issues observed on G52 in Amlogic G12B SoCs. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Steven Price <steven.price@arm.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Signed-off-by:
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Neil Armstrong authored
The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM, G12A/SM1 & G12B SoCs needs a quirk in the PWR registers at the GPU reset time. Since the Amlogic's integration of the GPU cores with the SoC is not publicly documented we do not know what does these values, but they permit having a fully functional GPU running with Panfrost. Signed-off-by:
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Neil Armstrong authored
The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM, G12A/SM1 & G12B SoCs needs a quirk in the PWR registers after each reset. This adds a callback in the device compatible struct of permit this. Signed-off-by:
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Daniel Vetter authored
We can now also delete drm_dev_init, now that vkms, vgem and i915 selftests are resolved. Reviewed-by:
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Luben Tuikov authored
Convert to using devm_drm_dev_alloc(), as drm_dev_init() is going away. v2: Remove drm_dev_put() since a) devres doesn't do refcounting, see Documentation/driver-api/driver-model/devres.rst, Section 4, paragraph 1; and since b) devres acts as garbage collector when the DRM device's parent's devres "action" callback is called to free the container device (amdgpu_device), which embeds the DRM dev. Acked-by:Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Daniel Vetter authored
To avoid having to create all the device and driver scaffolding we just manually create and destroy a devres_group. v2: Rebased v3: use devres_open/release_group so we can use devm without real hacks in the driver core or having to create an entire fake bus for testing drivers. Might want to extract this into helpers eventually, maybe as a mock_drm_dev_alloc or test_drm_dev_alloc. v4: - Fix IS_ERR handling (Matt) - Delete surplus put_device() in mock_device_release (intel-gfx-ci) v5: - do not switch to device_add - it breaks runtime pm in the tests and with the devres_group_add/release no longer needed for automatic cleanup (CI). Update commit message to match. - print correct error in pr_err (Matt) v6: Remove now unused err variable (CI). v7: More warning fixes ... Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v3) Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com> (v4) Signed-off-by:
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Daniel Vetter authored
Just some prep work before we rework the lifetime handling, which requires replacing all the drm_dev_put in selftests by something else. v2: Don't go with a static inline, upsets the header tests and separation. Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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- 18 Sep, 2020 2 commits
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Jing Xiangfeng authored
Remove the superfluous break, as there is a 'return' before it. Fixes: bad07ff7 ("fbcon: smart blitter usage for scrolling") Signed-off-by:
Jing Xiangfeng <jingxiangfeng@huawei.com> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Reviewed-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Vaibhav Gupta authored
The changes made in below mentioned commit removed CONFIG_PM containers from drivers/video/fbdev/aty/atyfb_base.c but not from drivers/video/fbdev/aty/atyfb.h for respective callbacks. This resulted in error for implicit declaration for those callbacks. Fixes: 348b2956 ("fbdev: aty: use generic power management") Signed-off-by:
Vaibhav Gupta <vaibhavgupta40@gmail.com> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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- 17 Sep, 2020 6 commits
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Dave Airlie authored
This was unused. Signed-off-by:
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Dave Airlie authored
The two accel cleanup paths were mostly the same once refactored. Just pass a bool to say if the evictions are to be pipelined. Signed-off-by:
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Dave Airlie authored
The pipeline and accel cleansups has similiar paths here. Signed-off-by:
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Dave Airlie authored
Both accel cleanup and pipeline move had the same code, make a single function for it. Signed-off-by:
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Dave Airlie authored
This pattern is called in a few places, just clean it up. Reviewed-by:
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Dave Airlie authored
Now the bind functions have all the protection explicitly the drivers can just call them directly, and the api can be unexported Reviewed-by:
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