- 24 Feb, 2016 10 commits
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Olof Johansson authored
Merge tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Renesas ARM Based SoC DT Updates for v4.6 * Use SCIF and USBHS fallback compatibility strings * Add Baud Rate Generator (BRG) support for (H)SCIF * Enable SCIF_CLK frequency and pins * Use GIC_* defines * Enable audio on r8a7793/gose * Enable HDMI vidio out on r8a7793 * Enable i2c on r8a7793/gose * Enable QSPI on alt * Enable GPIO keys and leds on gise * Enable audio on porter * Enable DU on porter * tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (68 commits) ARM: dts: silk: Enable SCIF_CLK frequency and pins ARM: dts: porter: Enable SCIF_CLK frequency and pins ARM: dts: marzen: Enable SCIF_CLK frequency and pins ARM: dts: lager: Enable SCIF_CLK frequency and pins ARM: dts: koelsch: Enable SCIF_CLK frequency and pins ARM: dts: gose: Enable SCIF_CLK frequency and pins ARM: dts: bockw: Enable SCIF_CLK frequency and pins ARM: dts: alt: Enable SCIF_CLK frequency and pins ARM: dts: r8a7794: Add BRG support for (H)SCIF ARM: dts: r8a7793: Add BRG support for SCIF ARM: dts: r8a7791: Add BRG support for (H)SCIF ARM: dts: r8a7790: Add BRG support for (H)SCIF ARM: dts: r8a7779: Add BRG support for SCIF ARM: dts: r8a7778: Add BRG support for SCIF ARM: dts: r8a7794: Rename the serial port clock to fck ARM: dts: r8a7793: Rename the serial port clock to fck ARM: dts: r8a7791: Rename the serial port clock to fck ARM: dts: r8a7790: Rename the serial port clock to fck ARM: dts: r8a7779: Rename the serial port clock to fck ARM: dts: r8a7778: Rename the serial port clock to fck ... Signed-off-by:
Olof Johansson <olof@lixom.net>
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Lars Persson authored
Signed-off-by:
Lars Persson <larper@axis.com> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Lars Persson authored
Initial device tree for the Artpec-6 SoC. Signed-off-by:
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Lars Persson authored
This adds device tree bindings for the Artpec-6 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Olof Johansson authored
Merge tag 'v4.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Assorted bunch of 32bit Rockchip devicetree changes. More clocks, nodes and fixes like the increased drive-strength on the firefly. Most interesting is maybe the enablement of the pl330 option for handling the broken flushp operation that is present on the current Rockchip SoCs. Together with the driver-side enablement this should give us working dma finally. * tag 'v4.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (30 commits) ARM: dts: cros-ec-keyboard: Add LOCK key to keyboard matrix ARM: dts: rockchip: replace gpio-key,wakeup with wakeup-source property ARM: dts: rockchip: add arm,pl330-broken-no-flushp quirk for rk3036 SoCs ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3xxx platform ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3288 platform dt-bindings: rockchip-dw-mshc: add RK3036 dw-mshc description ARM: dts: rockchip: increase the mclk_fs to 512 for kylin board ARM: dts: rockchip: support the spi for rk3036 ARM: dts: rockchip: add mclk for rt5616 on rk3036 kylin board ARM: dts: rockchip: add the leds control for rk3036-kylin board ARM: dts: rockchip: add tsadc node clk: rockchip: Add new id for rk3066 tsadc clock ARM: dts: rockchip: add clock-cells for usb phy nodes ARM: dts: rockchip: Assign RK3288 EDP_24M input centrally ARM: dts: rockchip: add soc-specific compatibles for rk3036 SoCs ARM: dts: rockchip: Bump sd card pin drive strength up on firefly boards dt-bindings: rockchip-dw-mshc: add RK3368 dw-mshc description ARM: dts: rockchip: Add the SDIO wifi on Radxa Rock2 square ARM: dts: rockchip: Add the iodomains for the Rock2 SOM ARM: dts: rockchip: add rk3288 mipi_dsi nodes ... Signed-off-by:
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Olof Johansson authored
Merge tag 'stm32-dt-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/dt Highlights: ----------- - Add DMA controller node to stm32f429 MCU - Add pinctrl & gpio nodes to stm32f429 MCU - Remap stm32429-eval board SD-Ram to 0x0 for performance boost * tag 'stm32-dt-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32: ARM: dts: stm32f429: Boost perfs by remapping SDRAM Bank 1 to 0x0 ARM: dts: Add leds support to STM32F429 boards ARM: dts: Add USART1 pin config to STM32F429 boards ARM: dts: Add pinctrl node to STM32F429 includes: dt-bindings: Add STM32F429 pinctrl DT bindings ARM: dts: Add STM32 DMA support for STM32F429 MCU Signed-off-by:
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Olof Johansson authored
Merge tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt Few updates for ARM VExpress/Juno platforms 1. GICv3 support on Foundation models 2. Support for Juno R2 board 3. Support for ARM HDLCD on all Juno platforms * tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: Add HDLCD support on Juno platforms Documentation: drm: Add DT bindings for ARM HDLCD arm64: dts: Add support for Juno r2 board arm64: dts: move juno pcie-controller to base file arm64: dts: add .dts for GICv3 Foundation model arm64: dts: split Foundation model dts to put the GIC separately arm64: dts: Foundation model: increase GICC region to allow EOImode=1 arm64: dts: prepare foundation-v8.dts to cope with GICv3 Signed-off-by:
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https://github.com/vzapolskiy/linuxOlof Johansson authored
Merge DT changes for lpc32xx from Vladimir Zapolskiy: "The changes add description of clock providers and clock consumers, define default irq types of SoC controllers and add PHY3250 board regulators. I'm adding an official LPC32xx maintainer Roland to Cc, however he seems to be unresponsive for a quite long time (since 2014)." * 'lpc32xx/dt' of https://github.com/vzapolskiy/linux: arm: dts: phy3250: add SD fixed regulator arm: dts: phy3250: add lcd and backlight fixed regulators arm: dts: lpc32xx: assign interrupt types arm: dts: lpc32xx: remove clock frequency property from UART device nodes arm: dts: lpc32xx: add USB clock controller arm: dts: lpc32xx: add clock properties to device nodes arm: dts: lpc32xx: add clock controller device node arm: dts: lpc32xx: add device nodes for external oscillators dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it Signed-off-by:
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Sudeep Holla authored
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup which is incorrect. Since the presence of the boolean property indicates it is enabled, value of "0" or "1" have no significance. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Reviewed-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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git://git.infradead.org/linux-mvebuOlof Johansson authored
mvebu dt for 4.6 (part 1) - Improve Armada 38x device tree (SATA and XHCI) - Fix SD Card and audio support for OpenRD board - Provide template for RS-232/485 configuration for the same board - Use a common dtsi file for linkstation boards - Add support for Buffalo Linkstation LS-QVL * tag 'mvebu-dt-4.6-1' of git://git.infradead.org/linux-mvebu: ARM: dts: kirkwood: add device tree for buffalo linkstation ls-qvl ARM: dts: kirkwood: fix audio for OpenRD clients ARM: dts: kirkwood: provide template for RS-232/485 configuration for OpenRD ARM: dts: kirkwood: split lswvl dts to linkstation lsvl and lswvl ARM: dts: kirkwood: split lswxl dts to linkstation lswsxl and lswxl ARM: dts: kirkwood: relicense dts of ls-wvl/vl and ls-wxl/wsxl under GPLv2/X11 ARM: dts: kirkwood: fix SD slot default configuration for OpenRD ARM: dts: kirkwood: fix pin names for UART/SD selection for OpenRD ARM: dts: armada-370: Update the mpp63 function in the device tree on Armada 370 ARM: dts: armada-38x: use usb-nop-xceiv PHY for the xhci nodes on Armada 388 GP ARM: dts: armada-38x: use regulator-boot-on for SATA regulators on Armada 388 GP ARM: dts: armada-38x: adjust board name and compatible for Armada 388 GP Signed-off-by:
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- 11 Feb, 2016 14 commits
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Maxime Coquelin authored
STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0, by writing 0x4 to SYSCFG_MEMRMP register. As mentionned in the reference manual (see chapter 9.3.1), the performance gain is really interresting: "In remap mode at address 0x0000 0000, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance." These are the dhrystone results with and without the remap enabled: Default (SDRAM in 0xc0000000): --------------------------------- Microseconds for one run through Dhrystone: 31.8 Dhrystones per Second: 31416.9 Remap (SDRAM in 0x0000000): ----------------------------- Microseconds for one run through Dhrystone: 20.6 Dhrystones per Second: 48520.1 This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL board, and also set the dma-range property as the other masters than the M4 CPU still see SDRAM in 0xc0000000. Note that the Discovery board cannot benefit from this feature, since the SDRAM is connected to Bank 2. Signed-off-by:Maxime Coquelin <mcoquelin.stm32@gmail.com>
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Maxime Coquelin authored
Acked-by:
Patrice Chotard <patrice.chotard@st.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Maxime Coquelin authored
This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Acked-by:
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Maxime Coquelin authored
The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank. Acked-by:
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Maxime Coquelin authored
Acked-by:
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Vladimir Zapolskiy authored
The change adds fixed voltage regulator for SD controller, ARM MMCI controller driver uses it to control card power management. Signed-off-by:Vladimir Zapolskiy <vz@mleia.com>
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Vladimir Zapolskiy authored
Phytec PHY3250 board has GPIO controlled regulators for LCD and backlight, add their descriptions to board DTS file. Signed-off-by: -
Vladimir Zapolskiy authored
LPC32xx interrupt controller has two cells, instead of zero specify proper irq types for all consumers. Signed-off-by: -
Vladimir Zapolskiy authored
If clock-frequency property is given, then it substitutes calculation of supplying clock frequency from parent clock, this may break UART, if parent clock is given and managed by common clock framework. Signed-off-by: -
Vladimir Zapolskiy authored
The change adds device node of LPC32xx USB clock controller and adds clock properties to USB OHCI, USB device and I2C controller to USB phy device nodes. Signed-off-by: -
Vladimir Zapolskiy authored
The change adds clock properties to all described peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Some existing drivers expect to get clock names, in those cases clock-names are added as well. Signed-off-by: -
Vladimir Zapolskiy authored
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part of system control block (SCB). CPC is supplied by two external oscillators and it manages core and most of peripheral clocks, the change adds SCB and CPC descriptions to shared LPC32xx dtsi file. Signed-off-by: -
Vladimir Zapolskiy authored
NXP LPC32xx SoC has two external oscillators - one is mandatory and always on 32768 Hz oscillator and one optional 10-20MHz oscillator, which is practically always present on LPC32xx boards, because its presence is needed to supply USB controller clock and by default it supplies ARM and most of the peripheral clocks, LPC32xx User's Manual references it as a main oscillator. The change adds device nodes for both oscillators, frequency of the main oscillator is selected to be 13MHz by default, this variant is found on all LPC32xx reference boards. The device nodes for external oscillators are needed to describe input clocks of LPC32xx clock controller. Signed-off-by: -
Vladimir Zapolskiy authored
Create a separate folder for device tree bindings of NXP SoCs devices, and move lpc32xx.txt to it. Acked-by:
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- 10 Feb, 2016 3 commits
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James Chao authored
The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices that use the Chrome OS EC keyboard matrix. Signed-off-by:
James Chao <james_chao@asus.com> Signed-off-by:
YH Huang <yh.huang@mediatek.com> Signed-off-by:
Daniel Kurtz <djkurtz@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Liviu Dudau authored
ARM's Juno platforms have two HDLCD controllers, each linked to an NXP TDA19988 HDMI transmitter that provides output encoding. Add them to the device tree. Acked-by:
Liviu Dudau <Liviu.Dudau@arm.com>
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Liviu Dudau authored
Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Acked-by:
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- 09 Feb, 2016 13 commits
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Sudeep Holla authored
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup and in one instance a value "0" is assigned probably assuming it won't be enabled as a wakeup source. Since the presence of the boolean property indicates it is enabled, value of "0" have no value. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates: - SCIF: - Supports now 50, 75, 110, 1152000, 1500000, 2000000, and 4000000 bps, - Perfect match for standard 50-460800, and 9216000 bps. - More accurate 576000 bps. - HSCIF: - Supports now 50, 75, 110, 134, 150, and 200 bps, - Perfect match for standard 50-460800, and 9216000 bps. - More accurate 576000, 1152000, 3000000, 3500000, and 4000000 bps. Signed-off-by:Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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