- 06 Jan, 2021 3 commits
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John Clements authored
sienna cichlid interfaces with RAS eeprom on I2C controller port 1 Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiaojian Du authored
This patch is to improve the fine grain tuning function for RV/RV2/PCO. This patch adds two new commands: "restore" and "commit". This function uses the pp_od_clk_voltage sysfs file to configure the min and max value of gfx clock frequency manually or restore the default value. Command guide: echo "s level value" > pp_od_clk_voltage "s" - set the sclk frequency "level" - 0 or 1, "0" represents the min value, "1" represents the max value "value" - the target value of sclk frequency, it should be limited in the safe range echo "r" > pp_od_clk_voltage "r" - reset the sclk frequency, restore the default value instantly echo "c" > pp_od_clk_voltage "c" - commit the min and max value of sclk frequency to the system only after the commit command, the target values set by "s" command will take effect. Example: 1)change power profile from "auto" to "manual" $ cat power_dpm_force_performance_level auto $ echo "manual" > power_dpm_force_performance_level $ cat power_dpm_force_performance_level manual 2)check the default sclk frequency $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz 3)use "s" -- set command to configure the min and max sclk frequency $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz 4)use "r" -- reset command to restore the min or max sclk frequency $ echo "r" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by:Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch is to correct the sensor value of power for vangogh. Signed-off-by:
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- 24 Dec, 2020 2 commits
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Dave Airlie authored
Merge tag 'amd-drm-fixes-5.11-2020-12-23' of git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-fixes-5.11-2020-12-23: amdgpu: - Vangogh SMU fixes - Arcturus gfx9 fixes - Misc display fixes - Sienna Cichlid SMU update - Fix S3 display memory leak - Fix regression caused by DP sub-connector support amdkfd: - Properly require pcie atomics for gfx10 Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201223204752.4019-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2020-12-22' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * dma-buf: Include <linux/vmalloc.h> for building on MIPS * komeda: Fix order of operation in commit tail; Fix NULL-pointer and out-of-bounds access; Cleanups * ttm: Fix an unused-function warning Signed-off-by:
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- 23 Dec, 2020 21 commits
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Stylon Wang authored
EDID parsing in S3 resume pushes new display modes to probed_modes list but doesn't consolidate to actual mode list. This creates a race condition when amdgpu_dm_connector_ddc_get_modes() re-initializes the list head without walking the list and results in memory leak. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=209987Acked-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
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Alex Deucher authored
This is not a scsi driver. Reviewed-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Alex Deucher authored
Fixes a crash in drm_object_property_set_value() because the property is not set for internal DP ports that connect to a bridge chips (e.g., DP to VGA or DP to LVDS). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210739 Fixes: 65bf2cf9 ("drm/amdgpu: utilize subconnector property for DP through atombios") Tested-By:
Kris Karas <bugs-a17@moonlit-rail.com> Cc: Oleg Vasilev <oleg.vasilev@intel.com> Signed-off-by:
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Evan Quan authored
This can suppress the annoying but unharmful prompts. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Josip Pavic authored
[Why & How] Add function to identify which MPCC is providing input to a specified OPP Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by:
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Jake Wang authored
[Why] We defer clock updates to after pipes have been programmed. In some instances we use DPPCLK that have been previously set to be "unused". This results in a brief window of time where underflow could occur. [How] During prepare bandwidth allow rn_update_clocks_update_dpp_dto to check each instance and compare previous clock to new clock. If new clock is higher than previous clock, program DPPDTO. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Acked-by:
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Yongqiang Sun authored
- restore lvtma_pwrseq_delay2 from vbios integrated info table - restore MVID/NVID after power up. - Enable timer wake up mask when enable timer interrupt. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Jake Wang authored
[Why] For certain timings, Renoir may underflow due to sr exit latency being too slow. [How] Updated wm table for renoir. Signed-off-by:
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Sung Lee authored
[WHY] DSC should only be acquired per OPP. Therefore, DSC should only be acquired for the top_pipe when ODM is enabled. Not doing this check may lead to acquiring more DSC's than needed when doing MPO + ODM Combine. [HOW] Only acquire DSC if pipe is top_pipe. Signed-off-by:
Sung Lee <sung.lee@amd.com> Acked-by:
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Aric Cyr authored
[Why] FP2 programming not happening when topology changes occur with multiple displays. [How] Ensure FP2 is programmed whenever global sync changes occur but wait for VACTIVE first to avoid underflow. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Eryk Brol authored
[Why] new_crtc_state is already dereferenced earlier in the function [How] Remove the check Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
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Michael Strauss authored
[WHY] Virtual signals were previously counted as a workaround to S0i2 hang which is fixed on Renoir. This blocks S0i3 diags testing. [HOW] Stop counting virtual signals as S0i2 hang is fixed on Renoir. Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] there is some garbage showing up during reboot test. Reason: SMU might handle display driver msg defered and driver will send next msg to SMU after 10ms timeout, once SMU FW handle previous msg, parameters are changed to next one, which result in a wrong value be programmed. [How] Extend timeout to 2s so SMU will have enough time to handle driver msg. Signed-off-by:
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Rizvi authored
[Why] Need driver to pass values of backlight ramp start and ramp reduction so that intensity can be ramped down appropriately. [How] Using abm_parameters structure to get these values from driver. Signed-off-by:
Rizvi <syerizvi@amd.com> Acked-by:
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Martin Tsai authored
[why] The sink count change HPD_IRQ will be ignored if the branch device has only DP DFP. [how] To remove the port type restriction. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Acked-by:
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Martin Tsai authored
[why] Some MST display may not report the internal panel to DEVICE_COUNT, that makes the check condition always failed. [how] To update this condition with the reported device count + 1 (because the immediate repeater's internal panel is possibly not included in DEVICE_COUNT) Signed-off-by:
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Wesley Chalmers authored
[WHY] HUBP blanking sequence on DCN30 requires us to check if HUBP is in blank and also toggle HUBP_DISABLE, which should instead be called HUBP_SOFT_RESET for what it does in HW. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Qingqing Zhuo authored
[why] handler is supposedly passed in as a function pointer; however, the entire struct amdgpu_dm_irq_handler_data gets from the list is used to check match. [how] use the interrupt_handler within amdgpu_dm_irq_handler_data for checking match. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by:
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Hawking Zhang authored
GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0 are only applicable to me0 pipe0. For ASICs that have gfx pipe removed, don't toggle those bits. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Hawking Zhang authored
The number of crtc should be 0 for ASICs that don't have display engine. Remove the unnecessary asic type check then. Signed-off-by:
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Hawking Zhang authored
Check number of gfx ring, rather than asic type, before cp gfx engine initialization so driver just need to make sure number of gfx ring is initialized correctly in gfx early_init phase. No need to add additional asic type check everywhere when there is new asic with gfx pipe removed. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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- 18 Dec, 2020 12 commits
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Carsten Haitzler authored
KASAN found this problem. find_first_bit() expects to look at a pointer pointing to a long, but we look at a u32 - this is going to be an issue with endianness but, KSAN already flags this as out-of-bounds stack reads. This fixes it by just importing inot a local long. Signed-off-by:
Carsten Haitzler <carsten.haitzler@arm.com> Acked-by:
Liviu Dudau <liviu.dudau@arm.com> Signed-off-by:
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Carsten Haitzler authored
komeda_component_get_old_state() technically can return a NULL pointer. komeda_compiz_set_input() even warns when this happens, but then proceeeds to use that NULL pointer to compare memory content there agains the new state to see if it changed. In this case, it's better to assume that the input changed as there is no old state to compare against and thus assume the changes happen anyway. Signed-off-by:
Steven Price <steven.price@arm.com> Acked-by:
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Carsten Haitzler authored
ret is not actually read after this (only written in one case then returned), so this assign line is useless. This removes that assignment. Signed-off-by:
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James Qian Wang authored
Komeda HW has no special, program the update to HW is done first, then flip happens. So correct the sequence to hw_done() first then flip_done(). Reported-by:
Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
James Qian Wang <james.qian.wang@arm.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Daniel Vetter authored
Merge tag 'drm-intel-next-fixes-2020-12-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 fixes for the merge window Signed-off-by:
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Christian König authored
That seems to be unused. Daniel: Mike reported a warning when booting with qxl, which this patch fixes: [ 1.815561] WARNING: CPU: 7 PID: 355 at drivers/gpu/drm/ttm/ttm_pool.c:365 ttm_pool_alloc+0x41b/0x540 [ttm] Signed-off-by:
Mike Galbraith <efault@gmx.de> Tested-by:
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Dave Airlie authored
As per the radeon/amdgpu fix don't use multihop if hw moves aren't enabled. Reported-by:
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Christian König authored
That seems to be unused. Signed-off-by:
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Aditya Swarup authored
Fix TGL REVID macros to fetch correct display/gt stepping based on SOC rev id from INTEL_REVID() macro. Previously, we were just returning the first element of the revid array instead of using the correct index based on SOC rev id. Fixes: c33298cb ("drm/i915/tgl: Fix stepping WA matching") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Aditya Swarup <aditya.swarup@intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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Chris Wilson authored
When inserting a VMA, we restrict the placement to the low 4G unless the caller opts into using the full range. This was done to allow usersapce the opportunity to transition slowly from a 32b address space, and to avoid breaking inherent 32b assumptions of some commands. However, for insert we limited ourselves to 4G-4K, but on verification we allowed the full 4G. This causes some attempts to bind a new buffer to sporadically fail with -ENOSPC, but at other times be bound successfully. commit 48ea1e32 ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page") suggests that there is a genuine problem with stateless addressing that cannot utilize the last page in 4G and so we purposefully excluded it. This means that the quick pin pass may cause us to utilize a buggy placement. Reported-by:
CQ Tang <cq.tang@intel.com> Testcase: igt/gem_exec_params/larger-than-life-batch Fixes: 48ea1e32 ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: CQ Tang <cq.tang@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Cc: <stable@vger.kernel.org> # v4.5+ Link: https://patchwork.freedesktop.org/patch/msgid/20201216092951.7124-1-chris@chris-wilson.co.uk (cherry picked from commit 5f22cc0b) Signed-off-by:
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Lionel Landwerlin authored
CI shows this workaround is also needed on Gen11. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 059a0beb ("drm/i915/perf: workaround register corruption in OATAILPTR") Reviewed-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201126105155.540350-1-lionel.g.landwerlin@intel.com (cherry picked from commit fa5d598b) Signed-off-by:
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Chris Wilson authored
We now use ilk_hpd_irq_setup for all GMCH platforms that do not have hotplug. These are early gen3 and gen2 devices that now explode on boot as they try to access non-existent registers. Fixes: 794d61a1 ("drm/i915: re-order if/else ladder for hpd_irq_setup") Signed-off-by:
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- 17 Dec, 2020 2 commits
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Alex Deucher authored
There is no reserveration so set the size to 0. Fixes a regression on SR-IOV. Reviewed-by:
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Xiaomeng Hou authored
Only pmfw version behind v4.63.23.00 could support this message. Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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