- 29 Feb, 2016 40 commits
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Russell King authored
Further simplify the code in sdhci_prepare_data() - we don't set SDHCI_REQ_USE_DMA anywhere else in the driver, so there is no need to set it, and then immediately test it. Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Tested-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Russell King authored
Rather than scanning the scatterlist multiple times for each quirk, scan it once, checking for each possible quirk. This should be cheaper due to the length and offset members commonly sharing the same cache line than scanning the scatterlist multiple times. Signed-off-by:
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Russell King authored
Prepare to consolidate the DMA address/size quirk handling into one single loop. Signed-off-by:
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Russell King authored
The patch "mmc: sdhci: plug DMA mapping leak on error" added un-mapping logic to sdhci_tasklet_finish() where it is always called, thereby preventing the mapping leaking. Consequently the un-mapping code in sdhci_finish_data() is no longer needed. Remove it. Signed-off-by:
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Russell King authored
Commit d31911b9 ("mmc: sdhci: fix dma memory leak in sdhci_pre_req()") added a complicated method to manage the DMA map state for the data transfer, but this complexity is not required. There are three states: * Unmapped * Mapped by sdhci_pre_req() * Mapped by sdhci_prepare_data() sdhci_prepare_data() needs to know when the data buffers have been successfully mapped by sdhci_pre_req(), and if so, there is no need to map them a second time. When we come to tear down the mapping, we want to know whether sdhci_post_req() will be called (which is determined by sdhci_pre_req() having been previously called) so that we can postpone the unmap operation. Hence, it makes sense to simply record when the successful DMA map happened (via COOKIE_PRE_MAPPED vs COOKIE_MAPPED) rather than having the complex mechanics involving COOKIE_MAPPED vs COOKIE_GIVEN. If a mapping is created by sdhci_prepare_data(), we must tear it down ourselves, without waiting for sdhci_post_req() (hence, the new COOKIE_MAPPED case). If the mapping is created by sdhci_pre_req() then sdhci_post_req() is responsible for tearing the mapping down. Signed-off-by:
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Russell King authored
If the host cookie indicates that the data buffers of a request are mapped at sdhci_post_req() time, always unmap the data buffers. Signed-off-by:
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Russell King authored
Pass the desired cookie for a successful map. This is in preparation to clean up the MAPPED/GIVEN states. Signed-off-by:
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Russell King authored
In sdhci_prepare_data(), when SDHCI_REQ_USE_DMA is set, there are two paths that prepare the data buffers for transfer. One is when SDHCI_USE_ADMA is set, and is located inside sdhci_adma_table_pre(). The other is when SDHCI_USE_ADMA is clear, in the else clause of the above. Factor out the call to sdhci_pre_dma_transfer() along with its error checking. Signed-off-by:
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Russell King authored
Move sdhci_pre_dma_transfer() to avoid needing to declare this function before use. Signed-off-by:
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Russell King authored
sdhci_finish_data() has two paths which result in identical DMA cleanup. One is when SDHCI_USE_ADMA is clear, and the other is just before when SDHCI_USE_ADMA is set, and is performed within sdhci_adma_table_post(). Simplify the code by removing the 'else' and eliminating the duplicate inside sdhci_adma_table_post(). Signed-off-by:
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Russell King authored
If we are writing data to the card, there is no point in walking the scatterlist to find out if there are any unaligned entries; this is a needless waste of CPU cycles. Avoid this by checking for a non-read tranfer first. Signed-off-by:
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Russell King authored
Signed-off-by:
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Russell King authored
Allocate both the alignment and DMA descriptor buffers together. The size of the alignment buffer will always be aligned to the hosts required alignment, which gives appropriate alignment to the DMA descriptors. We have a maximum of 128 segments, and a maximum alignment of 64 bits. This gives a maximum alignment buffer size of 1024 bytes. The DMA descriptors are a maximum of 12 bytes, and we allocate 128 * 2 + 1 of these, which gives a maximum DMA descriptor buffer size of 3084 bytes. This means the allocation for a 4K page sized system will be an order-1 allocation, since the resulting overall size is 4108. This is more prone to failure than page-sized allocations, but since this allocation commonly occurs at startup, the chances of failure are small. Signed-off-by:
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Russell King authored
The calculation for the timeout based on the number of card clocks is incorrect. The calculation assumed: timeout in microseconds = clock cycles / clock in Hz which is clearly a several orders of magnitude wrong. Fix this by multiplying the clock cycles by 1000000 prior to dividing by the Hz based clock. Also, as per part 1, ensure that the division rounds up. As this needs 64-bit math via do_div(), avoid it if the clock cycles is zero. Signed-off-by:
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Russell King authored
The data timeout gives the minimum amount of time that should be waited before timing out if no data is received from the card. Simply dividing the nanosecond part by 1000 does not give this required guarantee, since such a division rounds down. Use DIV_ROUND_UP() to give the desired timeout. Signed-off-by:
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Russell King authored
sdhci_post_req() exists to unmap a previously mapped but already finished request, while the next request is in progress. However, the state of the SDHCI_REQ_USE_DMA flag depends on the last submitted request. This means we can end up clearing the flag due to a quirk, which then means that sdhci_post_req() fails to unmap the DMA buffer, potentially leading to data corruption. We can safely ignore the SDHCI_REQ_USE_DMA here, as testing data->host_cookie is entirely sufficient. Signed-off-by:
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Russell King authored
Commit 1140011e ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") broke any chance of the SDR50 or DDR50 modes being used. The commit claims that SDR50 and DDR50 require clock adjustments in the SDIO3 Configuration register, which is located via the "conf-sdio3" resource. However, when this resource is given, we fail to read the host capabilities 1 register, resulting in host->caps1 being zero. Hence, both SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50 bits remain zero, disabling the SDR50 and DDR50 modes. The underlying idea in this function appears to be to read the device capabilities, modify them, and set SDHCI_QUIRK_MISSING_CAPS to cause our modified capabilities to be used. Implement exactly that. Fixes: 1140011e ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") Signed-off-by:
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Russell King authored
If we terminate a command early, we fail to properly clean up the DMA mappings for the data part of the request. Put this clean up to the tasklet, which is the common path for finishing a request so we always clean up after ourselves. Signed-off-by:
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Russell King authored
Unnecessarily mapping and unmapping the align buffer for SD cards is expensive: performance measurements on iMX6 show that this gives a hit of 10% on hdparm buffered disk reads. MMC/SD card IO comes from the mm/vfs which gives us page based IO, so for this case, the align buffer is not going to be used. However, we still map and unmap this buffer. Eliminate this by switching the align buffer to be a DMA coherent buffer, which needs no DMA maintenance to access the buffer. Signed-off-by:
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Russell King authored
When we get a response CRC error on a command, it means that the response we received back from the card was not correct. It does not mean that the card did not receive the command correctly. If the command is one which initiates a data transfer, the card can enter the data transfer state, and start sending data. Moreover, if the request contained a data phase, we do not clean this up, and this results in the driver triggering DMA API debug warnings, and also creates a race condition in the driver, between running the finish_tasklet and the data transfer interrupts, which can trigger a "Got data interrupt" state dump. Fix this by handing a response CRC error slightly differently: record the failure of the data initiating command, but allow the remainder of the request to be processed normally. This is safe as core MMC checks the status of all commands and data transfer phases of the request. If the card does not initiate a data transfer, then we should time out according to the data transfer parameters. Signed-off-by:
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Russell King authored
Avoid multiple tests while handling a command error; simplify the code. Signed-off-by:
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Russell King authored
When a command is started, logically it has no error. Initialise the command's error member to zero whenever we start a command. Signed-off-by:
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Ulf Hansson authored
up the maintainer role for SDHCI. I am very pleased that Adrian Hunter volunteered and accepted the challenge! The SDHCI code is currently in quite poor quality, but we have agreed on a way forward to try to reach a point where the SDHCI core becomes more of a set of library functions. Each SDHCI driver variant can then decide which functions to use and allows it to implement variant specific code, without needing to also change SDHCI core code. In the end we aim to get better optimized and maintainable code. Signed-off-by:
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Al Cooper authored
sdhci_add_host() allows the Host Controller Capability registers to be supplied by the calling driver by using SDHCI_QUIRK_MISSING_CAPS, but the check for the Capabilities bit SDHCI_CAN_64BIT doesn't use the applied value and instead reads the Host register directly. This change uses the supplied "caps" register instead of reading the host register. This change will allow a calling driver to simply clear the SDHCI_CAN_64BIT bit in "caps" to handle some cases of SDHCI_QUIRK2_BROKEN_64_BIT_DMA. Signed-off-by:
Al Cooper <alcooperx@gmail.com> Acked-by:
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Andrei Pistirica authored
This driver supports the SDHCI host controller found on a PIC32. Signed-off-by:
Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by:
Joshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
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Andrei Pistirica authored
Document the devicetree bindings for the SDHCI peripheral found on Microchip PIC32 class devices. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Shawn Lin authored
This patch make num_slots to 1 if pdata->num_slot is not defined. Meanwhile, we need to make sure num_slots should not larger that the supported slots Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
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Shawn Lin authored
dw_mci_probe clear interrupts and disable all interrupts firstly. While it clear interrupt again before enable some interrupts. We can't see any reason to clear it twice here, so remove the second one. Signed-off-by:
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Shawn Lin authored
This patch add correct err handle if dw_mci_ctrl_reset failed while probing. Signed-off-by:
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Shawn Lin authored
dw_mmc already use mmc_of_parse to get "broken-cd" property, but it considered "broken-cd" to be a quirk in its driver. We don't need this quirk here, and just take what we need from mmc->caps. Signed-off-by:
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Shawn Lin authored
This patch removes struct block_settings since it's never used anywhere. Signed-off-by:
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Shawn Lin authored
This patch implement hw_reset function for DesignWare MMC controller. By adding this feature, mmc blk can do some basic recovery. Set the following resets: software reset – BMOD[0] for IDMAC only DMA reset - CTRL[2] FIFO reset - CTRL[1] bits Program the CARD_RESET register with a value of 0 for the bit corresponding to the card number; This programming asserts the RST_n signal and resets the card. After a minimum of 1 ?s, de-asserts the RST_n signal and takes the card out of reset. The application can program a new CMD only after a minimum of 200 us This implementation can be easily tested by cutting off->On vmmc while doing data accessing in background to simulate that case. Signed-off-by:
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Jaehoon Chung authored
This patch removes the prepare_command hook from entire dw_mmc driver. Now, almost all SoCs are using by default, except Exynos. It seems that dwmmc controller is using unnecessary hook. To know whether needs to set this bit or not, add the DW_MMC_CARD_NO_USE_HOLD bit. If some SoCs need to disable this in future, just set the DW_MMC_CARD_NO_USE_HOLD bit. set_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags), Signed-off-by:
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Russell King authored
Print the error code when the tuning command fails. This allows the reason for the failure to be reported, which aids debugging. Signed-off-by:
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Russell King authored
Re-tuning is part of standard requirements for the higher speed SD card protocols, and is not an error when this occurs. When we retry a command due to a retune, we should not print a message to the kernel log. Signed-off-by:
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Russell King authored
Improve mmc_of_parse_voltage()'s return values so that drivers can tell whether a voltage-range specification was present, and whether it has been successfully parsed, or there was an error while parsing. We return a negative errno when parsing fails, zero if no voltage-range specification is present, or one if a voltage-range specification is successfully parsed. No users need modifying as no users check the return value. Signed-off-by:
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Russell King authored
Each time a driver such as sdhci-esdhc-imx is probed, we get a info printk complaining that the DT voltage-ranges property has not been specified. However, the DT binding specifically says that the voltage-ranges property is optional. That means we should not be complaining that DT hasn't specified this property: by indicating that it's optional, it is valid not to have the property in DT. Silence the warning if the property is missing. Signed-off-by:
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Wolfram Sang authored
Rcar2 & 3 docs state that for going to and coming from the 0xff setting, the clock must first be disabled before the DIV bits are changed. Instead of tracking this, let's just do this unconditionally. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Wolfram Sang authored
Some of the indentation made the code awful to read. Fix that. Also, introduce defines instead of magic hex values. Note that this includes one change: We mask out know 0xff instead of 0x1ff. But 0x100 has always been the clock enable bit. It doesn't make any sense to set it depending on the clock calculation. Update copyright notices, too. I'll be working on those files some more in the future. Signed-off-by:
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Wolfram Sang authored
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